Abstract: This patent discloses novel design and implementations of high-performance and scalable Montgomery modular multiplier circuits by utilizing and developing a combination of optimization techniques and dataflow transformations including use of carry-save compressions, multiplier decomposition using a radix of 2m, multiplicand decomposition using a radix of 2w, parallelization of computations of the quotient and intermediate results in each iteration of the Montgomery modular multiplication, replacement of multiplications and additions in each iteration with simple encoding and compression operations, and correction of potential overflows in intermediate results by doing a simple 2-bit addition.