Patents by Inventor Zen-Jay Tsai
Zen-Jay Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869953Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.Type: GrantFiled: September 13, 2022Date of Patent: January 9, 2024Assignee: UNITED MICROELECTRONICS CORPInventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
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Patent number: 11721702Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.Type: GrantFiled: June 20, 2022Date of Patent: August 8, 2023Assignee: United Microelectronics Corp.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Chung-Liang Chu, Zen-Jay Tsai, Yu-Hsiang Lin
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Publication number: 20230207692Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.Type: ApplicationFiled: March 2, 2023Publication date: June 29, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
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Patent number: 11626515Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.Type: GrantFiled: December 2, 2020Date of Patent: April 11, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
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Publication number: 20230006048Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.Type: ApplicationFiled: September 13, 2022Publication date: January 5, 2023Inventors: Sheng-Yao HUANG, Yu-Ruei CHEN, Zen-Jay TSAI, Yu-Hsiang LIN
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Patent number: 11476343Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.Type: GrantFiled: March 26, 2021Date of Patent: October 18, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
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Publication number: 20220320147Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.Type: ApplicationFiled: June 20, 2022Publication date: October 6, 2022Applicant: United Microelectronics Corp.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Chung-Liang Chu, Zen-Jay Tsai, Yu-Hsiang Lin
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Patent number: 11417685Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.Type: GrantFiled: November 29, 2019Date of Patent: August 16, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Chung-Liang Chu, Zen-Jay Tsai, Yu-Hsiang Lin
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Publication number: 20220238673Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.Type: ApplicationFiled: March 26, 2021Publication date: July 28, 2022Inventors: Sheng-Yao HUANG, Yu-Ruei CHEN, Zen-Jay TSAI, Yu-Hsiang LIN
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Publication number: 20220140139Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.Type: ApplicationFiled: December 2, 2020Publication date: May 5, 2022Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
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Publication number: 20210104554Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.Type: ApplicationFiled: November 29, 2019Publication date: April 8, 2021Applicant: United Microelectronics Corp.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Chung-Liang Chu, Zen-Jay Tsai, Yu-Hsiang Lin
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Patent number: 8841181Abstract: A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.Type: GrantFiled: March 7, 2012Date of Patent: September 23, 2014Assignee: United Microelectronics Corp.Inventors: Ying-Hung Chou, Shao-Hua Hsu, Chi-Horn Pai, Zen-Jay Tsai, Shih-Hao Su, Chun-Chia Chen, Shih-Chieh Hsu, Chih-Chung Chen
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Patent number: 8709930Abstract: A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.Type: GrantFiled: November 25, 2011Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Zen-Jay Tsai, Shao-Hua Hsu, Chi-Horn Pai, Ying-Hung Chou, Shih-Hao Su, Shih-Chieh Hsu, Chih-Ho Wang, Hung-Yi Wu, Shui-Yen Lu
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Publication number: 20130234216Abstract: A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ying-Hung Chou, Shao-Hua Hsu, Chi-Horn Pai, Zen-Jay Tsai, Shih-Hao Su, Chun-Chia Chen, Shih-Chieh Hsu, Chih-Chung Chen
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Publication number: 20130137256Abstract: A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.Type: ApplicationFiled: November 25, 2011Publication date: May 30, 2013Inventors: Zen-Jay Tsai, Shao-Hua Hsu, Chi-Horn Pai, Ying-Hung Chou, Shih-Hao Su, Shih-Chieh Hsu, Chih-Ho Wang, Hung-Yi Wu, Shui-Yen Lu
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Patent number: 8278166Abstract: A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.Type: GrantFiled: July 16, 2010Date of Patent: October 2, 2012Assignee: United Microelectronics Corp.Inventors: Chun-Chia Chen, Ying-Hung Chou, Zen-Jay Tsai, Shih-Chieh Hsu, Yi-Chung Sheng, Chi-Horn Pai
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Publication number: 20120012938Abstract: A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.Type: ApplicationFiled: July 16, 2010Publication date: January 19, 2012Inventors: Chun-Chia Chen, Ying-Hung Chou, Zen-Jay Tsai, Shih-Chieh Hsu, Yi-Chung Sheng, Chi-Horn Pai