Abstract: The present invention provides a graphene structure having graphene bubbles and a preparation method for the same. The preparation method comprises: providing a substrate; forming a hydrogen terminated layer on a top surface of the substrate and a graphene layer disposed on a top surface of the hydrogen terminated layer; and placing a probe on the graphene layer and applying a preset voltage to the probe, to excite a part of the hydrogen terminated layer at a position corresponding to the probe to convert into hydrogen, the hydrogen causing the graphene layer at a position corresponding to the hydrogen to bulge, so as to form a graphene bubble enveloping the hydrogen.

Abstract: The present disclosure provides a field-effect transistor structure and a method for fabricating the same. The method comprises: providing a substrate, and depositing at least one first material layer and at least one second material layer on a surface of the substrate; defining an active region and a shallow trench isolation region; etching the active region to form a channel region, a source region and a drain region; corroding the first material layer or second material layer in the groove region to obtain at least one nano-wire channel; depositing a dielectric layer and a gate structure layer on a surface of nano-wire channel; and fabricating a gate electrode, a source electrode and a drain electrode on surfaces of the gate structure layer, the source region and the drain region to complete the fabrication of the field-effect transistor.

Abstract: The present invention provides a graphene structure having graphene bubbles and a preparation method for the same. The preparation method comprises: providing a substrate; forming a hydrogen terminated layer on a top surface of the substrate and a graphene layer disposed on a top surface of the hydrogen terminated layer; and placing a probe on the graphene layer and applying a preset voltage to the probe, to excite a part of the hydrogen terminated layer at a position corresponding to the probe to convert into hydrogen, the hydrogen causing the graphene layer at a position corresponding to the hydrogen to bulge, so as to form a graphene bubble enveloping the hydrogen.

Abstract: The invention belongs to the technical field of inorganic compounds, and particularly, relates to a method for directly preparing graphene by taking CBr4 as a source material and using methods such as molecular-beam epitaxy (MBE) or chemical vapor deposition (CVD). A method for preparing graphene comprises the following steps: selecting a proper material as a substrate; directly depositing a catalyst and CBr4 on a surface of the substrate; and performing annealing treatment on the sample obtained through deposition. Compared with other technologies, an innovative point of the method in the invention is that the catalyst and CBr4 source can be quantitatively and controllably deposited on any substrate, and the catalyst and CBr4 source react on the surface of the substrate to form the graphene, so that the dependence of the graphene growth on a substrate material can be reduced to a great extent, and different substrate materials can be selected according to different application backgrounds.

Abstract: A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form fluorinated graphene; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; and 4) forming a metal electrode on the surface of the high-k gate dielectric. Since the present invention utilizes the graphene as a passivation layer to inhibit the formation of unstable oxide GeOx on the surface of the Ge-based substrate and to stop mutual diffusion between the gate dielectric and the Ge-based substrate, the interface property between Ge and the high-k gate dielectric layer is improved.

Abstract: A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form fluorinated graphene; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; and 4) forming a metal electrode on the surface of the high-k gate dielectric. Since the present invention utilizes the graphene as a passivation layer to inhibit the formation of unstable oxide GeOx on the surface of the Ge-based substrate and to stop mutual diffusion between the gate dielectric and the Ge-based substrate, the interface property between Ge and the high-k gate dielectric layer is improved.

Abstract: The present invention provides a method for preparing an ultra-thin material on insulator through adsorption by a doped ultra-thin layer. In the method, first, an ultra-thin doped single crystal film and an ultra-thin top film (or contains a buffer layer) are successively and epitaxially grown on a first substrate, and then a high-quality ultra-thin material on insulator is prepared through ion implantation and a bonding process. A thickness of the prepared ultra-thin material on insulator ranges from 5 nm to 50 nm. In the present invention, the ultra-thin doped single crystal film adsorbs the implanted ion, and a micro crack is then formed, so as to implement ion-cut; therefore, the roughness of a surface of a ion-cut material on insulator is small.

Abstract: Provided is a method for preparing a material on an insulator based on enhanced adsorption. In the method: first, a single crystal film having a doped superlattice structure, an intermediate layer, a buffer layer and a top layer film are epitaxially grown in succession on a first substrate; then, low dosage ion implantation is performed on the structure on which the top layer film is formed, so that ions are implanted above an upper surface or below a lower surface of the single crystal film having a doped superlattice structure; next, a second substrate having an insulation layer is bonded to the structure on which ion implantation has already been performed, and an annealing treatment is performed, so that a microscopic crack is produced at the single crystal film having a doped superlattice structure to achieve atomic-scale stripping. The effective stripping of bonding wafers is achieved by means of enhanced adsorption.

Abstract: The invention belongs to the technical field of inorganic compounds, and particularly, relates to a method for directly preparing graphene by taking CBr4 as a source material and using methods such as molecular-beam epitaxy (MBE) or chemical vapor deposition (CVD). A method for preparing graphene comprises the following steps: selecting a proper material as a substrate; directly depositing a catalyst and CBr4 on a surface of the substrate; and performing annealing treatment on the sample obtained through deposition. Compared with other technologies, an innovative point of the method in the invention is that the catalyst and CBr4 source can be quantitatively and controllably deposited on any substrate, and the catalyst and CBr4 source react on the surface of the substrate to form the graphene, so that the dependence of the graphene growth on a substrate material can be reduced to a great extent, and different substrate materials can be selected according to different application backgrounds.

Abstract: The present invention provides a method for preparing an ultra-thin material on insulator through adsorption by a doped ultra-thin layer. In the method, first, an ultra-thin doped single crystal film and an ultra-thin top film (or contains a buffer layer) are successively and epitaxially grown on a first substrate, and then a high-quality ultra-thin material on insulator is prepared through ion implantation and a bonding process. A thickness of the prepared ultra-thin material on insulator ranges from 5 nm to 50 nm. In the present invention, the ultra-thin doped single crystal film adsorbs the implanted ion, and a micro crack is then formed, so as to implement ion-cut; therefore, the roughness of a surface of a ion-cut material on insulator is small.

Abstract: The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a SMART CUT technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.

Abstract: A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects.

Abstract: A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects.

Abstract: The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a Smart-Cut technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.

Abstract: The present invention provides a semiconductor structure with a hybrid of Ge and a group III-V material coplanar and a preparation method thereof. A heterogeneously integrated semiconductor structure with Ge and a group III-V semiconductor material coplanar includes at least one Ge substrate formed on a bulk silicon substrate, and the other substrate is the group III-V semiconductor material formed on the Ge semiconductor.

Abstract: The present invention provides a device system structure based on hybrid orientation SOI and channel stress and a preparation method thereof. According to the preparation method provided in the present invention, first, a (100)/(110) global hybrid orientation SOI structure is prepared; then, after epitaxially growing a relaxed silicon-germanium layer and strained silicon layer sequentially on the global hybrid orientation SOI structure, an (110) epitaxial pattern window is formed; then, after epitaxially growing a (110) silicon layer and a non-relaxed silicon-germanium layer at the (110) epitaxial pattern window, a surface of the patterned hybrid orientation SOI structure is planarized; then, an isolation structure for isolating devices is formed; and finally, a P-type high-voltage device structure is prepared in a (110) substrate portion, an N-type high-voltage device structure and/or low voltage device structures are prepared in the (100) substrate portion.

Abstract: A preparation method for a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations and a preparation method of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) based on the method are disclosed. In the preparation method for the full-isolated SOI substrate with hybrid crystal orientations provided in the present invention, a SiGe layer is adopted to serve as an epitaxial virtual substrate layer with a first crystal orientation, so as to form a strained top silicon with the first crystal orientation; a polysilicon supporting material is adopted to serve as a support for connecting the top silicon with the first crystal orientation and a top silicon with a second crystal orientation, so that the SiGe layer below the strained top silicon with the first crystal orientation may be removed, and an insulating material is filled to form an insulating buried layer.

Abstract: A preparation method for a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations and a preparation method of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) based on the method are disclosed. In the preparation method for the full-isolated SOI substrate with hybrid crystal orientations provided in the present invention, a SiGe layer is adopted to serve as an epitaxial virtual substrate layer with a first crystal orientation, so as to form a strained top silicon with the first crystal orientation; a polysilicon supporting material is adopted to serve as a support for connecting the top silicon with the first crystal orientation and a top silicon with a second crystal orientation, so that the SiGe layer below the strained top silicon with the first crystal orientation may be removed, and an insulating material is filled to form an insulating buried layer.

Abstract: The present invention provides an SOI semiconductor structure with a hybrid of coplanar germanium (Ge) and III-V, and a method for preparing the same. A heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar on an insulator includes at least one Ge substrate formed on the insulating layer, and the other substrate is a group III-V semiconductor material formed on the Ge semiconductor.