Abstract: A method, device, system, and storage medium for tracking a moving target are provided. The method uses three-dimensional radar observation data to construct a state vector and a motion model of the moving target, thereby to construct a state equation and an observation equation for achieving filtering and tracking within a linear Gaussian framework. The disclosure is also suitable for a moving target in a two-dimensional scene with a distance and an azimuth, and the disclosure use a two-dimensional observation vector to construct a dynamic system to achieving tracking of the moving target. The disclosure can be used in radar systems containing Doppler measurements, and tracking of moving targets can be implemented by performing dimension-expansion processing on observation equations.

Abstract: The present disclosure provides a target mounting fixture, including: a target fixing frame for fixing a target, the target fixing frame including a hoisting portion; a target carrier detachably connected to the target fixing frame; and a moving unit connected to the target carrier for moving the target carrier to move the target.

Abstract: The present disclosure provides a target mounting fixture, including: a target fixing frame for fixing a target, the target fixing frame including a hoisting portion; a target carrier detachably connected to the target fixing frame; and a moving unit connected to the target carrier for moving the target carrier to move the target.

Abstract: The present disclosure provides a TFT, an array substrate, their manufacturing methods, and a display device. A source electrode and a drain electrode of the TFT are each of a multi-layered structure including a metal layer and a metal barrier layer. An a-Si active layer of the TFT is covered with an etch stop layer, via-holes penetrating through the etch stop layer are provided at positions corresponding to the source electrode and the drain, and the source electrode and the drain electrode are connected to the a-Si active layer through the via-holes.

Abstract: A method for manufacturing an array substrate includes coating a photoresist onto an insulation layer including a gate insulation layer and an etch stop layer, wherein the gate insulation layer covers a conductive pattern and the etch stop layer covers a semiconductive pattern. The method further includes exposing the photoresist to form a photoresist partially-reserved region and a photoresist unreserved region. The method further includes performing a first etching process to at least partially remove a portion of the insulation layer located at a position corresponding to the photoresist unreserved region, to form an intermediate hole. The method further includes performing a second etching process to form the first via hole and form the second via hole at a position of the intermediate hole, thereby to reveal the semiconductive pattern and the conductive pattern at positions corresponding to the first via hole and the second via hole, respectively.

Abstract: The present disclosure provides a TFT, an array substrate, their manufacturing methods, and a display device. A source electrode and a drain electrode of the TFT are each of a multi-layered structure including a metal layer and a metal barrier layer. An a-Si active layer of the TFT is covered with an etch stop layer, via-holes penetrating through the etch stop layer are provided at positions corresponding to the source electrode and the drain, and the source electrode and the drain electrode are connected to the a-Si active layer through the via-holes.

Abstract: A method for manufacturing an array substrate includes steps of: coating a photoresist onto an insulation layer covered with a conductive pattern and/or a semiconductive pattern; exposing the photoresist to form at least a photoresist partially-reserved region corresponding to a region where a first via hole is formed, and a photoresist unreserved region corresponding to a region where a second via hole is formed; performing a first etching process so as to at least partially remove a portion of the insulation layer located at a position corresponding to the photoresist unreserved region, thereby to form an intermediate hole; and performing a second etching process, so as to form the first via hole, and form the second via hole at a position of the intermediate hole, thereby to reveal the semiconductive pattern and/or the conductive pattern at positions corresponding to the first via hole and the second via hole, respectively.