Patents by Inventor Zengrong Li

Zengrong Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261225
    Abstract: Provided is an oxide thin film transistor, including a gate, a gate insulator, a channel layer, a protective layer, and a source electrode and drain electrode layer that are disposed on a base substrate, wherein the source electrode and drain electrode layer includes a source electrode and a drain electrode that are spaced; and the protective layer is disposed between the channel layer and the source electrode and drain electrode layer, and is in contact with both the source electrode and drain electrode layer and the channel layer; an orthographic projection of the protective layer on the base substrate covers an orthographic projection of the channel layer on the base substrate; and the protective layer includes a first portion, a second portion, and a third portion that are in different areas of the protective layer.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: March 25, 2025
    Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bin Lin, Zengrong Li, Hangle Guo, Zhenyou Zou, Liangliang Li, Fadian Le
  • Publication number: 20250015091
    Abstract: Provided is an array substrate. The array substrate includes: a substrate, and a first electrode, a connecting electrode, and at least two insulating layers arranged on the substrate, wherein the first electrode is disposed on a side, proximal to the first electrode, of the at least two insulating layers, and the connecting electrode is disposed on a side, facing away from the substrate, of the at least two insulating layers; and at least two communicated vias are arranged in the at least two insulating layers, a size of a first via, most proximal to the substrate, in the at least two vias is less than sizes of other vias, and the connecting electrode is lapped with the first electrode via the at least two vias.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 9, 2025
    Applicants: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Bin LIN, Yang WANG, Jinliang WANG, Qiming LI, Zhenyou ZOU, Zengrong LI
  • Publication number: 20240258326
    Abstract: A display substrate, manufacturing method thereof, and a display device. The display substrate includes a base substrate and a semiconductor layer and a conductive layer on the base substrate. The semiconductor layer includes a channel region and a doped region pattern of a transistor; the conductive layer includes a data line, and a first electrode and a second electrode of the transistor. An extension direction of an overlapping portion of the semiconductor layer with the data line is the same as an extension direction of the data line, and the semiconductor layer includes a first protrusion portion, and a size of an interval between an edge of the first protrusion portion away from the data line and the edge of the data line is greater than 0 and smaller than 3.0 microns.
    Type: Application
    Filed: November 30, 2021
    Publication date: August 1, 2024
    Inventors: Wanxia FU, Liangliang LI, Xiaolong CHEN, Zhouyu CHEN, Bin LIN, Zengjie LIN, Zengrong LI
  • Publication number: 20240234440
    Abstract: Disclosed is a preparation method for an array substrate including: forming a first conductive portion on a substrate; sequentially forming a first insulating layer, a second insulating layer and a third insulating layer on the side of the first conductive portion that faces away from the substrate; forming, through one-time patterning process, a first sub-via that penetrates through the third insulating layer, the second insulating layer and a first part of the first insulating layer; forming a fourth insulating layer on the side of the third insulating layer that faces away from the substrate; etching and removing the fourth insulating layer and the first insulating layer of the second thickness that are at the first sub-via, so as to form a first via; and forming a first connection electrode on the side of the fourth insulating layer that faces away from the substrate.
    Type: Application
    Filed: July 1, 2022
    Publication date: July 11, 2024
    Inventors: Bin LIN, Yang WANG, Liangliang LI, Zengrong LI, Hangle GUO, Wenxing XI
  • Publication number: 20240170579
    Abstract: Provided is an oxide thin film transistor, including a gate, a gate insulator, a channel layer, a protective layer, and a source electrode and drain electrode layer that are disposed on a base substrate, wherein the source electrode and drain electrode layer includes a source electrode and a drain electrode that are spaced; and the protective layer is disposed between the channel layer and the source electrode and drain electrode layer, and is in contact with both the source electrode and drain electrode layer and the channel layer; an orthographic projection of the protective layer on the base substrate covers an orthographic projection of the channel layer on the base substrate; and the protective layer includes a first portion, a second portion, and a third portion that are in different areas of the protective layer.
    Type: Application
    Filed: December 1, 2020
    Publication date: May 23, 2024
    Inventors: Bin Lin, Zengrong Li, Hangle Guo, Zhenyou Zou, Liangliang Li, Fadian Le
  • Patent number: 11927861
    Abstract: A display panel and a display device are disclosed, relating to the display technical field. The display panel comprises a display layer and a light control layer which are laminated, the light control layer comprises a plurality of light control pixel areas, the light control pixel areas comprise a thin film transistor, the display layer comprises a plurality of display pixel areas, and the display pixel areas comprise a green sub-pixel; the orthographic projection of the green sub-pixel on the light control pixel area is close to the area where the thin film transistor is located.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: March 12, 2024
    Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Renhui Yu, Wen Zha, Xin Chen, Hongzhou Xie, Shangtao Zheng, Meizhen Chen, Ying Tian, Zengrong Li, Ye Hu, Qingna Hou, Kai Diao
  • Publication number: 20230002854
    Abstract: A new method for extracting lithium from salt lake brine, comprising the following steps: a salt lake old brine raw material, desorption liquid, low-magnesium water, and adsorption tail liquid pass through an old brine feeding pipe (2), a desorption liquid feeding pipe (4), a low-magnesium water top desorption liquid feeding pipe (3), and an adsorption tail liquid top desorption liquid feeding pipe (11), respectively, which are located above and below a rotary disc of a multi-way valve system (1); and after respectively entering corresponding adsorption columns (6) by means of a duct and channel within the multi-way valve system (1), the entire process procedure is completed from an adsorption tail liquid discharge pipe (7), a qualified desorption liquid discharge pipe (10), a lithium-containing old brine discharge pipe (8), and an adsorption tail liquid top desorption liquid discharge pipe (5); and the adsorption columns (6) are connected in series or in parallel by means of channels located in the multi-way
    Type: Application
    Filed: December 16, 2020
    Publication date: January 5, 2023
    Applicants: SUNRESIN NEW MATERIALS CO. LTD., MINMETALS SALT LAKE CO., LTD.
    Inventors: Jia YU, Zengrong LI, Dayi ZHANG, Fumin GUO, Zhaofei HOU, Faman TANG, Mian WANG, Zhibo LUO, Chao ZAN, Suidang LI, Qiong LIU, Yongxiao SONG, Yun WANG, Xiaokang KOU
  • Publication number: 20220390782
    Abstract: A display panel and a display device are disclosed, relating to the display technical field. The display panel comprises a display layer and a light control layer which are laminated, the light control layer comprises a plurality of light control pixel areas, the light control pixel areas comprise a thin film transistor, the display layer comprises a plurality of display pixel areas, and the display pixel areas comprise a green sub-pixel; the orthographic projection of the green sub-pixel on the light control pixel area is close to the area where the thin film transistor is located.
    Type: Application
    Filed: May 18, 2021
    Publication date: December 8, 2022
    Applicants: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE Technology Group Co., Ltd.
    Inventors: Renhui Yu, Wen Zha, Xin Chen, Hongzhou Xie, Shangtao Zheng, Meizhen Chen, Ying Tian, Zengrong Li, Ye Hu, Qingna Hou, Kai Diao
  • Patent number: D1015406
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: February 20, 2024
    Inventors: ZengRong Li, Yun Chen
  • Patent number: D1043597
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: September 24, 2024
    Inventor: ZengRong Li