Patents by Inventor Zengtao “Tony” Liu

Zengtao “Tony” Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit fabrication
    Patent number: 8507341
    Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: August 13, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, John Lee, Zengtao “Tony” Liu, Eric Freeman, Russell Nielsen
  • Integrated circuit fabrication
    Patent number: 8158476
    Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: April 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, John Lee, Zengtao “Tony” Liu, Eric Freeman, Russell Nielsen
  • Integrated circuit fabrication
    Patent number: 7776683
    Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: August 17, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, John Lee, Zengtao “Tony” Liu, Eric Freeman, Russell Nielsen
  • Integrated circuit fabrication
    Patent number: 7648919
    Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: January 19, 2010
    Inventors: Luan C. Tran, John Lee, Zengtao “Tony” Liu, Eric Freeman, Russell Nielsen
  • Integrated circuit fabrication
    Patent number: 7611944
    Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: November 3, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, John Lee, Zengtao “Tony” Liu, Eric Freeman, Russell Nielsen