Patents by Inventor Zengyi Yuan

Zengyi Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11307151
    Abstract: The present disclosure discloses a method for detecting a wafer backside defect, comprising: Step 1, providing a signal database comprising signal data corresponding to various different defects, the defects comprising convex defects and concave defects, the signal data reflecting 3D information of the corresponding defect; Step 2, performing backside scanning on a tested wafer by using oblique incident light, and collecting corresponding emitted and scattered light data; and Step 3, comparing the collected emitted and scattered light data with the signal data, and fitting a defect 3D distribution map of the backside of the tested wafer. The present disclosure can test the height or depth of a wafer backside defect and form a 3D distribution map of the wafer backside defect, which is beneficial for analyzing the source of the wafer backside defect and processing it in time, reducing the troubleshooting time and improving the product yield.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: April 19, 2022
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventors: Zengyi Yuan, Yin Long, Kai Wang
  • Publication number: 20210063320
    Abstract: The present disclosure discloses a method for detecting a wafer backside defect, comprising: Step 1, providing a signal database comprising signal data corresponding to various different defects, the defects comprising convex defects and concave defects, the signal data reflecting 3D information of the corresponding defect; Step 2, performing backside scanning on a tested wafer by using oblique incident light, and collecting corresponding emitted and scattered light data; and Step 3, comparing the collected emitted and scattered light data with the signal data, and fitting a defect 3D distribution map of the backside of the tested wafer. The present disclosure can test the height or depth of a wafer backside defect and form a 3D distribution map of the wafer backside defect, which is beneficial for analyzing the source of the wafer backside defect and processing it in time, reducing the troubleshooting time and improving the product yield.
    Type: Application
    Filed: June 2, 2020
    Publication date: March 4, 2021
    Applicant: Shanghai Huali Integrated Circuit Corporation
    Inventors: Zengyi Yuan, Yin Long, Kai Wang