Patents by Inventor Zengyu Zhou
Zengyu Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11917761Abstract: A surface mount device having features on contacts to prevent the surface mount device from tombstoning. The feature may be channel defined by the contact that helps balance a torque/force applied on each side of the surface mount device during a reflow soldering process. The feature may also be a solder mask that helps balance a torque/force applied on each side of the surface mount device during a reflow soldering process.Type: GrantFiled: March 7, 2022Date of Patent: February 27, 2024Assignee: Western Digital Technologies, Inc.Inventors: Joyce Chen, Lynn Lin, Emma Wang, Linda Huang, Cong Zhang, Zengyu Zhou, Juan Zhou
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Patent number: 11810896Abstract: A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.Type: GrantFiled: May 18, 2021Date of Patent: November 7, 2023Assignee: Western Digital Technologies, Inc.Inventors: Jiandi Du, Zengyu Zhou, Rui Yuan, Fen Yu, Hope Chiu
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Patent number: 11784135Abstract: A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.Type: GrantFiled: June 22, 2021Date of Patent: October 10, 2023Assignee: Western Digital Technologies, Inc.Inventors: Jiandi Du, Binbin Zheng, Rui Guo, Chin-Tien Chiu, Zengyu Zhou, Fen Yu
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Publication number: 20230299034Abstract: A semiconductor device package includes a semiconductor die including bond pads and an underfill inlet side, a substrate including a first metal layer and lower metal layers underneath the first metal layer, a plurality of metal contacts and trace segment lines disposed in the first metal layer, and a plurality of solder bump rows. Each of the solder bump rows is oriented substantially parallel to the inlet side of the semiconductor die and electrically connects bond pads of the semiconductor die with corresponding metal contacts in the first metal layer of the substrate. Each of the trace segment lines is oriented substantially parallel to the inlet side of the semiconductor die, is electrically coupled to a respective solder bump row of the plurality of solder bump rows, and includes trace segments disposed in the first metal layer and trace segments disposed in one or more of the lower metal layers.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Applicant: Western Digital Technologies, Inc.Inventors: Yihao Chen, Tim Huang, Zengyu Zhou, Rui Yuan, Fen Yu, Hope Chiu
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Publication number: 20230284388Abstract: A surface mount device having features on contacts to prevent the surface mount device from tombstoning. The feature may be channel defined by the contact that helps balance a torque/force applied on each side of the surface mount device during a reflow soldering process. The feature may also be a solder mask that helps balance a torque/force applied on each side of the surface mount device during a reflow soldering process.Type: ApplicationFiled: March 7, 2022Publication date: September 7, 2023Inventors: Joyce Chen, Lynn Lin, Emma Wang, Linda Huang, Cong Zhang, Zengyu Zhou, Juan Zhou
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Publication number: 20220406726Abstract: A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.Type: ApplicationFiled: June 22, 2021Publication date: December 22, 2022Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Jiandi Du, Binbin Zheng, Rui Guo, Chin-Tien Chiu, Zengyu Zhou, Fen Yu
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Publication number: 20220375896Abstract: A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Inventors: Jiandi DU, Zengyu ZHOU, Rui YUAN, Fen YU, Hope CHIU
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Publication number: 20220285316Abstract: A memory device includes a substrate, a controller die, a flip chip die, first and second silicon dies, and bond wires. The controller and flip chip dies are attached to the substrate using connection balls and in electrical communication with each other. The first and second silicon dies include respective first and second contact pad surfaces. The bond wires electrically connect the contact pad surfaces to the substrate so the first and second silicon dies communicate with the controller die. The flip chip die and first and second silicon dies are NAND dies, the flip chip die is configured as SLC memory, and the silicon dies are configured as one of MLC memory, TLC memory, or QLC memory.Type: ApplicationFiled: March 4, 2021Publication date: September 8, 2022Inventors: Rui Yuan, Hope Chiu, Paul Qu, Kevin Du, Zengyu Zhou, Yi Su, Shixing Zhu
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Publication number: 20220093559Abstract: A packaged semiconductor includes a substrate and a first component disposed on the substrate. The package includes an underfill that is dispensed under and around the first component. The package also includes a second component disposed on the substrate adjacent to the first component that provides a border to the underfill.Type: ApplicationFiled: September 22, 2020Publication date: March 24, 2022Applicant: Western Digital Technologies, Inc.Inventors: Kevin Du, Hope Chiu, Zengyu Zhou, Alex Zhang, Vincent Jiang, Shixing Zhu, Paul Qu, Yi Su, Rui Yuan
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Patent number: 11031378Abstract: A semiconductor device is disclosed including a controller die and a memory module. The controller die may be a heterogeneous integrated controller die having ASIC logic circuits, memory array logic circuits and a cache structure. In examples, the memory module may have continuously formed through silicon vias in a face-up or face-down configuration.Type: GrantFiled: March 13, 2020Date of Patent: June 8, 2021Assignee: Western Digital Technologies, Inc.Inventors: Yazhou Zhang, Chin-Tien Chiu, Zengyu Zhou
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Publication number: 20200411479Abstract: A semiconductor device is disclosed including a controller die and a memory module. The controller die may be a heterogeneous integrated controller die having ASIC logic circuits, memory array logic circuits and a cache structure. In examples, the memory module may have continuously formed through silicon vias in a face-up or face-down configuration.Type: ApplicationFiled: March 13, 2020Publication date: December 31, 2020Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yazhou Zhang, Chin-Tien Chiu, Zengyu Zhou
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Patent number: 10236276Abstract: A semiconductor device is disclosed including at least first and second vertically stacked and interconnected groups of semiconductor packages. The first and second groups of semiconductor packages may differ from each other in the number of packages and functionality.Type: GrantFiled: June 12, 2017Date of Patent: March 19, 2019Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.Inventors: Yangming Liu, Chin-Tien Chiu, Zhongli Ji, Shaopeng Dong, Zengyu Zhou
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Patent number: 10177119Abstract: A semiconductor package is disclosed including a number of stacked semiconductor die, electrically connected to each other with wire bonds. The stacked semiconductor die are provided in a mold compound such that a spacing exists between a top die in the die stack and a surface of the mold compound. The wire bonds to the top die may be provided in the spacing. An RDL pad is affixed to the surface of the mold compound. Columns of bumps may be formed on the die bond pads of the top die in the die stack to electrically couple the RDL pad to the die stack across the spacing.Type: GrantFiled: June 12, 2017Date of Patent: January 8, 2019Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.Inventors: Cong Zhang, Fuqiang Xiao, Bin Xu, Haijun Wu, Chin Tien Chiu, Zengyu Zhou
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Publication number: 20180294251Abstract: A semiconductor device is disclosed including at least first and second vertically stacked and interconnected groups of semiconductor packages. The first and second groups of semiconductor packages may differ from each other in the number of packages and functionality.Type: ApplicationFiled: June 12, 2017Publication date: October 11, 2018Applicant: SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD.Inventors: Yangming Liu, Chin-Tien Chiu, Zhongli Ji, Shaopeng Dong, Zengyu Zhou
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Publication number: 20180019228Abstract: A semiconductor package is disclosed including a number of stacked semiconductor die, electrically connected to each other with wire bonds. The stacked semiconductor die are provided in a mold compound such that a spacing exists between a top die in the die stack and a surface of the mold compound. The wire bonds to the top die may be provided in the spacing. An RDL pad is affixed to the surface of the mold compound. Columns of bumps may be formed on the die bond pads of the top die in the die stack to electrically couple the RDL pad to the die stack across the spacing.Type: ApplicationFiled: June 12, 2017Publication date: January 18, 2018Applicant: SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD .Inventors: Cong Zhang, Fuqiang Xiao, Bin Xu, Haijun Wu, Chin Tien Chiu, Zengyu Zhou