Patents by Inventor Zensuke Matsuda

Zensuke Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5132569
    Abstract: An input circuit is responsive to a TTL-level input signal for producing a CMOS-level output signal and the complementary signal thereof and comprises a first inverter circuit implemented by a series combination of a p-channel type field effect transistor, a first output node and an n-p-n type bipolar transistor and responsive to the TTL-level input signal and a control signal opposite in phase to the input signal for producing the CMOS-level complementary output signal, a second inverter circuit implemented by a series combination of n-channel type field effect transistors and responsive to the input signal for producing the control signal, and a third inverter circuit implemented by a series combination of a p-channel type field effect transistor and an n-channel type field effect transistor and responsive to the CMOS-level complementary output signal for producing the CMOS-level output signal at a second output node, wherein the p-channel type field effect transistor of the first inverter circuit is enlarg
    Type: Grant
    Filed: November 15, 1990
    Date of Patent: July 21, 1992
    Assignee: NEC Corporation
    Inventor: Zensuke Matsuda
  • Patent number: 4150311
    Abstract: A differential type amplifier circuit for use as a sensing amplifier in a memory circuit having a first stage amplifier and a second stage differential type amplifier. The first stage amplifier includes a pair of amplification circuits, the inputs of which are selectively clamped to a predetermined potential. The first stage amplifier functions to amplify low level differential input signals and these amplified signals are applied to the second stage amplifier, the amplified level of the input signals being sufficient to operate the second stage amplifier irrespective of changes in the threshold voltage of the second stage amplifier. Selectively clamping the inputs of the first stage amplifier to a predetermined potential allows the first stage amplifier to accurately amplify the low level input signals due to the fact that the threshold voltage of the first stage amplifier cannot vary from the predetermined potential.
    Type: Grant
    Filed: October 12, 1977
    Date of Patent: April 17, 1979
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Zensuke Matsuda, Shigeru Koshimaru