Patents by Inventor Zenya Fujii

Zenya Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7149912
    Abstract: When controlling a clock to a central processing unit, it is naturally preferable not to change existing circuits which are not related to the control of the clock. A clock control circuit inputs a clock input CLK, and generates a clock output CLKOUT for the central processing unit. In the clock control circuit, CLK is masked by a write operation to an internal register. CLKOUT is stopped by the mask operation. The mask operation is carefully designed to be initiated when the internal cycle of the central processing unit is detected. The resumption of the clock is initiated by interrupts.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: December 12, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Zenya Fujii
  • Patent number: 6810471
    Abstract: There are provided a plurality of priority register circuits which specify respective priorities for a plurality of logical regions, so that the priority of the logical regions can be varied. Even if there is a change in a memory map, the degree of freedom for setting changes is high compared to a case when the priority is fixed. Thus, the purpose can be attained more likely by a processing of changing the priority where the processing involves comparatively low number of bits.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: October 26, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Zenya Fujii
  • Publication number: 20030163752
    Abstract: When controlling a clock to a central processing unit, it is naturally preferable not to change existing circuits which are not related to the control of the clock. A clock control circuit inputs a clock input CLK, and generates a clock output CLKOUT for the central processing unit. In the clock control circuit, CLK is masked by a write operation to an internal register. CLKOUT is stopped by the mask operation. The mask operation is carefully designed to be initiated when the internal cycle of the central processing unit is detected. The resumption of the clock is initiated by interrupts.
    Type: Application
    Filed: February 20, 2003
    Publication date: August 28, 2003
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventor: Zenya Fujii
  • Publication number: 20020199076
    Abstract: There are provided a plurality of priority register circuits which specify respective priorities for a plurality of logical regions, so that the priority of the logical regions can be varied. Even if there is a change in a memory map, the degree of freedom for setting changes is high compared to a case when the priority is fixed. Thus, the purpose can be attained more likely by a processing of changing the priority where the processing involves comparatively low number of bits.
    Type: Application
    Filed: June 24, 2002
    Publication date: December 26, 2002
    Applicant: Sanyo Electric Co. Ltd.
    Inventor: Zenya Fujii