Patents by Inventor Zerui Chen

Zerui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250038976
    Abstract: A lattice-based proxy signature method, apparatus and device, a lattice-based proxy signature verification method, apparatus and device, and a storage medium. Polynomials are randomly selected in rings to calculate public and private keys of nodes, and the magnitudes of proxy public and private keys are the same as the magnitudes of public and private keys of an original signer. Therefore, compared with existing proxy signature schemes, the present application has smaller lengths of public and private keys and higher storage efficiency. Proxy signature information generated in the present application shows a signature of the original signer and also shows a signature of a proxy signer. Once a proxy signature is created, the proxy signature cannot be repudiated by the proxy signer, and has strong non-repudiation and strong unforgeability. The proxy signature method has the advantage of resisting quantum computer attack.
    Type: Application
    Filed: August 18, 2022
    Publication date: January 30, 2025
    Applicants: ELECTRIC POWER RESEARCH INSTITUTE, CHINA SOUTHERN POWER GRID, GUIZHOU POWER GRID CO., LTD.
    Inventors: Bin QIAN, Houpeng HU, Yong XIAO, Jiaxiang OU, Mi ZHOU, Pengcheng LI, Yi LUO, Yanhong XIAO, Ji WANG, Xin WU, Fusheng LI, Peilin HE, Xiaoming LIN, Zhenghao GAO, Jianlin TANG, Zerui CHEN, Fan ZHANG, Gaoyi LONG, Qiang CHANG, Qin FENG, Yuanhong CEN
  • Publication number: 20240273649
    Abstract: A trusted anonymous voting method includes: performing a hash operation on original voting content to obtain a hash output including a commitment value cvi; blinding the commitment value cvi based on information of other voters to obtain commitment value tuples {tilde over (c)} and {tilde over (x)}; signing the commitment value tuple {tilde over (c)} by using an ESDSA to obtain a signature tuple {tilde over (s)}; and establishing a vote tuple ({tilde over (c)}, {tilde over (s)}, {tilde over (d)}) based on the commitment value tuple {tilde over (c)}, the signature tuple {tilde over (s)} and a signature tuple {acute over (d)} of other voters, and uploading the vote tuple (?, ?, {acute over (d)}) and the commitment value tuple {tilde over (x)} to the blockchain, where signature tuple {tilde over (d)} is generated in a case that other voters verify the signature tuple {tilde over (s)} and the signature tuple {tilde over (s)} passes the verification, and the commitment value tuple {tilde over (x)} is used to decry
    Type: Application
    Filed: September 2, 2022
    Publication date: August 15, 2024
    Applicants: ELECTRIC POWER RESEARCH INSTITUTE, CHINA SOUTHERN POWER GRID, GUIZHOU POWER GRID CO., LTD.
    Inventors: Yong XIAO, Jiaxiang OU, Yi LUO, Houpeng HU, Bin QIAN, Peilin HE, Mi ZHOU, Yaodan DENG, Ji WANG, Tianqiang DONG, Fusheng LI, Pengcheng LI, Fan ZHANG, Yanhong XIAO, Xiaoming LIN, Gaoyi LONG, Jianlin TANG, Kunlin HE, Chaoying LIU, Hangfeng LI, Zerui CHEN
  • Patent number: 7847315
    Abstract: A high-efficiency power semiconductor rectifier device (10) comprising a ?P++ layer (12), a P-body (14), an N-drift region (16), an N+ substrate (18), an anode (20), and a cathode (22). The method of fabricating the device (10) comprises the steps of depositing the N-drift region (16) on the N+ substrate (18), implanting boron into the N-drift region (16) to create a P-body region (14), forming a layer of titanium silicide (56) on the P-body region (14), and concentrating a portion of the implanted boron at the interface region between the layer of titanium silicide (56) and the P-body region (14) to create the ?P++ layer (12) of supersaturated P-doped silicon.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: December 7, 2010
    Assignee: Diodes Fabtech Inc.
    Inventors: Roman J. Hamerski, Zerui Chen, James Man-Fai Hong, Johnny Duc Van Chiem, Christopher D. Hruska, Timothy Eastman
  • Publication number: 20080217721
    Abstract: A high-efficiency power semiconductor rectifier device (10) comprising a ?P++ layer (12), a P-body (14), an N-drift region (16), an N+ substrate (18), an anode (20), and a cathode (22). The method of fabricating the device (10) comprises the steps of depositing the N-drift region (16) on the N+ substrate (18), implanting boron into the N-drift region (16) to create a P-body region (14), forming a layer of titanium silicide (56) on the P-body region (14), and concentrating a portion of the implanted boron at the interface region between the layer of titanium silicide (56) and the P-body region (14) to create the ?P++ layer (12) of supersaturated P-doped silicon.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 11, 2008
    Inventors: Roman J. Hamerski, Zerui Chen, James Man-Fai Hong, Johnny Duc Van Chiem, Christopher D. Hruska, Timothy Eastman