Patents by Inventor Zevnep M. Toros

Zevnep M. Toros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Software programmable verification tool having multiple built-in self-test (BIST) modules for testing and debugging multiple devices under test (DUT)
    Patent number: 7464295
    Abstract: Aspects of the invention may include testing and debugging an embedded device under test. Testing and debugging and embedded device under test may include the step of loading an instruction into a parameterized shift register of each one of a plurality of BIST modules coupled to an individual one of a plurality of embedded memory modules comprising the embedded device under test. An identity of each of the instruction loaded into the parameterized shift register of each one of the plurality of BIST modules may subsequently be determined. A separate test signal may be generated from each one of the plurality of BIST modules corresponding to the determined identity of the instruction loaded in each one of the plurality of BIST modules, each one of the generated test signals causing control and execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules comprising the embedded device under test.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: December 9, 2008
    Assignee: Broadcom Corporation
    Inventors: Zevnep M. Toros, Esin Terzioglu, Gil Winograd
  • Software programmable verification tool having multiple built-in self-test (BIST) modules for testing and debugging multiple devices under test (DUT)
    Publication number: 20040073840
    Abstract: Aspects of the invention may include testing and debugging an embedded device under test. Testing and debugging and embedded device under test may include the step of loading an instruction into a parameterized shift register of each one of a plurality of BIST modules coupled to an individual one of a plurality of embedded memory modules comprising the embedded device under test. An identity of each of the instruction loaded into the parameterized shift register of each one of the plurality of BIST modules may subsequently be determined. A separate test signal may be generated from each one of the plurality of BIST modules corresponding to the determined identity of the instruction loaded in each one of the plurality of BIST modules, each one of the generated test signals causing control and execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules comprising the embedded device under test.
    Type: Application
    Filed: October 11, 2002
    Publication date: April 15, 2004
    Inventors: Zevnep M. Toros, Esin Terzioglu, Gil Winograd