Patents by Inventor Zhan Chai

Zhan Chai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9953118
    Abstract: The present invention provides a modeling method of a SPICE model series of a Silicon On Insulator (SOI) Field Effect Transistor (FET), where auxiliary devices are designed and fabricated, electrical property data is measured, intermediate data is obtained, model parameters are extracted based on the intermediate data, a SPICE model of an SOI FET of a floating structure is established, model parameters are extracted by using the intermediate data and data of the auxiliary devices, a macro model is complied, and a SPICE model of an SOI FET of a body leading-out structure is established.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: April 24, 2018
    Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Jing Chen, Qingqing Wu, Jiexin Luo, Zhan Chai, Xi Wang
  • Patent number: 9134361
    Abstract: The present invention provides a method for determining BSIMSOI4 Direct Current (DC) model parameters, where a plurality of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices of a body leading-out structure and of different sizes, and a plurality of MOSFET devices of a floating structure and of different sizes are provided; Id-Vg-Vp, Id/Ip-Vd-Vg, Ig-Vg-Vd, Ig-Vp, Ip-Vg-vd, Is/Id-Vp, and Id/Ip-Vp-Vd properties of all the MOSFET devices of a body leading-out structure, and Id-Vg-Vp, Id-Vd-Vg, and Ig-Vg-Vd properties of all the MOSFET devices of a floating structure are measured; electrical property curves without a self-heating effect of each MOSFET device of a body leading-out structure and each MOSFET device of a floating structure are obtained; and then DC parameters of a BSIMSOI4 model are successively extracted according to specific steps.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: September 15, 2015
    Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Jing Chen, Qingqing Wu, Jiexin Luo, Zhan Chai, Xi Wang
  • Patent number: 8667440
    Abstract: A calibration method for a device using TCAD to emulation SOI field effect transistor, where process emulation MOS device structures with different channel lengths Lgate are obtained by establishing a TCAD process emulation program; the process emulation MOS device structures are calibrated according to a TEM test result, a SIMS test result, a CV test result, a WAT test result, and a square resistance test result of an actual device, so as to complete TCAD emulation calibration of key electrical parameters of an SOI field effect transistor. Thereby, providing effective guidance for research, development and optimization of a new process flow are realized.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: March 4, 2014
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Zhan Chai, Jing Chen, Jiexin Luo, Qingqing Wu, Xi Wang
  • Publication number: 20130152033
    Abstract: The present invention provides a Technology Computer Aided Design (TCAD) emulation calibration method of a Silicon On Insulator (SOI) field effect transistor, where process emulation Metal Oxide Semiconductor (MOS) device structures with different channel lengths Lgate are obtained by establishing a TCAD process emulation program; based on the process emulation MOS device structures, the process emulation MOS device structures are calibrated according to a Transmission Electron Microscope (TEM) test result, a secondary ion mass spectrometer (SIMS) test result, a Capacitor Voltage (CV) test result, a WAT test result, and a square resistance test result of an actual device, so as to complete TCAD emulation calibration of key electrical parameters of an SOI field effect transistor.
    Type: Application
    Filed: September 23, 2011
    Publication date: June 13, 2013
    Applicant: SHANGHAI OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMY
    Inventors: Zhan Chai, Jing Chen, Jiexin Luo, Qingqing Wu, Xi Wang
  • Publication number: 20130054219
    Abstract: The present invention provides an equivalent electrical model of a Silicon On Insulator (SOI) Field Effect Transistor (FET) of a body leading-out structure, and a modeling method thereof. The equivalent electrical model is formed by an internal FET and an external FET connected in parallel, where the SOI FET of a body leading-out structure is divided into a body leading-out part and a main body part, the internal FET represents a parasitic transistor of the body leading-out part, and the external FET represents a normal transistor of the main body part. The equivalent electrical model provided in the present invention completely includes the influence of parts of a physical structure of the SOIMOSFET device of a body leading-out structure, that is, the body leading-out part and the main body part, on the electrical properties, thereby improving a fitting effect of the model on the electrical properties of the device.
    Type: Application
    Filed: September 25, 2011
    Publication date: February 28, 2013
    Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOOGY, CHINESE ACADEMY
    Inventors: Jing Chen, Qingqing Wu, Jiexin Luo, Zhan Chai, Xi Wang
  • Publication number: 20130054209
    Abstract: The present invention provides a modeling method of a SPICE model series of a Silicon On Insulator (SOI) Field Effect Transistor (FET), where auxiliary devices are designed and fabricated, electrical property data is measured, intermediate data is obtained, model parameters are extracted based on the intermediate data, a SPICE model of an SOI FET of a floating structure is established, model parameters are extracted by using the intermediate data and data of the auxiliary devices, a macro model is complied, and a SPICE model of an SOI FET of a body leading-out structure is established.
    Type: Application
    Filed: September 25, 2011
    Publication date: February 28, 2013
    Inventors: Jing Chen, Qingqing Wu, Jiexin Luo, Zhan Chai, Xi Wang
  • Publication number: 20130054210
    Abstract: The present invention provides a method for determining BSIMSOI4 Direct Current (DC) model parameters, where a plurality of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices of a body leading-out structure and of different sizes, and a plurality of MOSFET devices of a floating structure and of different sizes are provided; Id-Vg-Vp, Id/Ip-Vd-Vg, Ig-Vg-Vd, Ig-Vp, Ip-Vg-vd, Is/Id-Vp, and Id/Ip-Vp-Vd properties of all the MOSFET devices of a body leading-out structure, and Id-Vg-Vp, Id-Vd-Vg, and Ig-Vg-Vd properties of all the MOSFET devices of a floating structure are measured; electrical property curves without a self-heating effect of each MOSFET device of a body leading-out structure and each MOSFET device of a floating structure are obtained; and then DC parameters of a BSIMSOI4 model are successively extracted according to specific steps.
    Type: Application
    Filed: September 25, 2011
    Publication date: February 28, 2013
    Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Jing Chen, Qingqing Wu, Jiexin Luo, Zhan Chai, Xi Wang