Abstract: A computing device includes last level cache (LLC) for processing cores and a separate input/output (I/O) LLC for use in facilitating data transfers between the computing device and one or more I/O devices. The I/O LLC is configured to include a set of partitions corresponding to a set of classes. Usage of the partitions in the set of partitions is monitored and the set of partitions is dynamically adjusted based on the usage. A process in a particular one of the classes makes a data request and a particular one of the partitions associated with the particular class is used in the data request.

Abstract: Examples described herein relate to an interface and circuitry. The circuitry can perform offloaded performance of a cryptographic handshake with a client in connection with initiation of a quick User Datagram Protocol Internet Connections (QUIC) connection with the client. In some examples, the cryptographic handshake comprises process a first client hello datagram from the client, the first client hello datagram is consistent with QUIC, and the offloaded performance of the cryptographic handshake with the client is offloaded from a processor to the circuitry.

Abstract: An electrostatic protection circuit includes: a monitoring circuit configured to generate a trigger signal in response to an electrostatic pulse being present on the power supply pad; a discharge transistor connected between the power supply pad and the ground pad and configured to be turned on under control of the trigger signal and discharge electrostatic discharging charges to the ground pad; and a delay circuit having an input terminal connected to an output terminal of the monitoring circuit, and an output terminal connected to a control terminal of the discharge transistor, where the delay circuit is configured to perform delay processing on the electrostatic protection circuit in a first state and turn off the discharge transistor in a second state.

Abstract: An electrostatic protection circuit includes: a monitoring circuit configured to generate a trigger signal in response to an electrostatic pulse being present on the power supply pad; a discharge transistor connected between the power supply pad and the ground pad and configured to be turned on under control of the trigger signal and discharge electrostatic discharging charges to the ground pad; and a delay circuit having an input terminal connected to an output terminal of the monitoring circuit, and an output terminal connected to a control terminal of the discharge transistor, where the delay circuit is configured to perform delay processing on the electrostatic protection circuit in a first state and turn off the discharge transistor in a second state.

Abstract: An Electro-Static Discharge (ESD) protection circuit includes a p-type substrate; a p-type well formed on the p-type substrate; a first Negative channel Metal Oxide Semiconductor (NMOS) transistor and a second NMOS transistor formed in the p-type well, where a drain of the first NMOS transistor is connected to a source of the second NMOS transistor; and a Lightly Doped Drain (LDD) region formed in proximity to a source of the first NMOS transistor.

Abstract: A memory management unit of a processor may receive a command associated with a process. The command may specify an operation to be performed by another device. The memory management unit may determine a counter value associated with a shared work queue of the another device, an indication the shared work queue to be specified by the command. The memory management unit may determine whether to accept or reject the command based on the counter value and a threshold for the process.