Abstract: Integrated circuits with a buried N layer and methods for fabricating such integrated circuits are provided. The method includes forming a buried N layer overlying a substrate, and forming a monocrystalline layer overlying the buried N layer. After forming the monocrystalline layer, a well tap trench is formed, where the well tap trench penetrates the electronics area and the buried N layer and extends into the substrate. A well tap is formed in the well tap trench.

Abstract: Integrated circuits with a buried N layer and methods for fabricating such integrated circuits are provided. The method includes forming a buried N layer overlying a substrate, and forming a monocrystalline layer overlying the buried N layer. After forming the monocrystalline layer, a well tap trench is formed, where the well tap trench penetrates the electronics area and the buried N layer and extends into the substrate. A well tap is formed in the well tap trench.

Abstract: In one embodiment of an LDMOS device disclosed herein, the device includes a source region, a drain region and a gate electrode that are formed in and above a semiconducting substrate, wherein the gate electrode is generally laterally positioned between the source region and the drain region, a metal-1 field plate positioned above the gate electrode, and a silicide block layer that is positioned in an area between the gate electrode and the drain region. The device further includes at least one source contact that is conductively coupled to the metal-1 field plate and a conductive structure that is conductively coupled to the metal-1 field plate, wherein at least a first portion of the conductive structure extends downward toward the substrate in the area between the gate electrode and the drain region.