Patents by Inventor Zhang Haiyang

Zhang Haiyang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996460
    Abstract: A semiconductor structure and a forming method thereof are provided, where one form of a forming method includes: providing a substrate, where the substrate includes a first region and a second region that are adjacent, stack structures are formed on the first region and the second region, and the stack structures of the first region and the second region and the substrate form a first opening; forming first dielectric layers on a bottom surface and side walls of the first opening, where a second opening is provided between the first dielectric layers; forming a second dielectric layer in the second opening; forming a source/drain doped layer; removing the first dielectric layer between the source/drain doped layer and the second dielectric layer, and forming a groove exposing a side wall, which is close to the second dielectric layer, of the source/drain doped layer; and forming a contact plug in the groove.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: May 28, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Ji Shiliang, Xiao Xingyu, Zhang Haiyang
  • Patent number: 11735429
    Abstract: Methods for forming a semiconductor structure are provided. In one form, a method includes: providing a base; forming an initial pattern layer on the base; and performing atomic layer etching processing on a sidewall of the initial pattern layer one or more times to form a pattern layer, where the atomic layer etching processing includes: forming an organic layer on the sidewall of the initial pattern layer; and removing the organic layer. Generally, bond energy between an atom on an outermost surface of the sidewall of the initial pattern layer and an atom at an inner layer is less than bond energy between the atom at the inner layer. The organic layer usually includes an element that may react with the sidewall of the initial pattern layer, further reducing the bond energy between the atom on the outermost surface of the sidewall of the initial pattern layer and the atom at the inner layer.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: August 22, 2023
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhang Haiyang, Liu Panpan, Yang Chenxi
  • Publication number: 20220102520
    Abstract: A semiconductor structure and a forming method thereof are provided, where one form of a forming method includes: providing a substrate, where the substrate includes a first region and a second region that are adjacent, stack structures are formed on the first region and the second region, and the stack structures of the first region and the second region and the substrate form a first opening; forming first dielectric layers on a bottom surface and side walls of the first opening, where a second opening is provided between the first dielectric layers; forming a second dielectric layer in the second opening; forming a source/drain doped layer; removing the first dielectric layer between the source/drain doped layer and the second dielectric layer, and forming a groove exposing a side wall, which is close to the second dielectric layer, of the source/drain doped layer; and forming a contact plug in the groove.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 31, 2022
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Ji SHILIANG, Xiao XINGYU, Zhang HAIYANG
  • Publication number: 20210225656
    Abstract: Methods for forming a semiconductor structure are provided. In one form, a method includes: providing a base; forming an initial pattern layer on the base; and performing atomic layer etching processing on a sidewall of the initial pattern layer one or more times to form a pattern layer, where the atomic layer etching processing includes: forming an organic layer on the sidewall of the initial pattern layer; and removing the organic layer. Generally, bond energy between an atom on an outermost surface of the sidewall of the initial pattern layer and an atom at an inner layer is less than bond energy between the atom at the inner layer. The organic layer usually includes an element that may react with the sidewall of the initial pattern layer, further reducing the bond energy between the atom on the outermost surface of the sidewall of the initial pattern layer and the atom at the inner layer.
    Type: Application
    Filed: December 2, 2020
    Publication date: July 22, 2021
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhang HAIYANG, Liu PANPAN, Yang CHENXI
  • Publication number: 20200211848
    Abstract: Disclosed are a semiconductor structure and a method for forming the same.
    Type: Application
    Filed: August 16, 2019
    Publication date: July 2, 2020
    Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Ji SHILIANG, Zhang YIYING, Zhang HAIYANG
  • Patent number: 10685838
    Abstract: Disclosed are a semiconductor structure and a method for forming the same.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventors: Ji Shiliang, Zhang Yiying, Zhang Haiyang
  • Patent number: 8835325
    Abstract: The present invention discloses a method of manufacturing a semiconductor device. In order to form a trench with a smaller width, patterns of various monomers are formed by utilizing self-assembly characteristics of a block copolymer comprising various monomers. A metal or metal nitride is deposited on a surface of the block copolymer, the metal or metallic nitride selectively depositing due to a preferential chemical affinity between various monomers and the metal or metal nitride. After reaching a certain thickness, the metal or metal nitride layer begins to grow laterally. Deposition can be stopped by controlling deposition time so that the metal or metal nitride layer grows laterally but does not completely cover the surface of the block copolymer. Etching is then conducted using the metal or metal nitride layer as a mask to obtain a trench with a very small width.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhang Haiyang, Minda Hu