Abstract: The present disclosure describes a semiconductor structure that is resistant to induced eddy currents. The semiconductor device includes a substrate, a device layer having electronic devices on the substrate, and a metallization layer above the device layer. The first metallization layer includes first and second terminal traces, a switch, and capacitors. A first terminal of a capacitor of the capacitors is coupled to the first terminal trace via the switch. A second terminal of the capacitor is coupled to the second terminal trace. The first and second terminal traces are disposed along the same side of the capacitors.

Abstract: A phase shifter circuit may include a multiple phase shifter cells (or cells) to selectively shift a phase of an input signal by a desired phase shift value. For example, each of the phase shifter cells may shift the phase of the input signal by a positive fractional phase shift value or a negative fractional phase shift value. The phase shifter cells may include circuitry to form an inductor-capacitor circuit to provide the negative fractional phase shift value and form a capacitor-inductor circuit to provide the positive fractional phase shift value. The phase shifter cells may receive control signals to form the inductor-capacitor circuit and the capacitor-inductor circuit. An electronic device may include multiple phase shifter circuits to adjust a phase of transmission signals and/or reception signals of phased array antennas.

Abstract: This disclosure is directed to a power combiner/divider with improved operating frequency range (e.g., bandwidth) compared to other power combiners/dividers. The power combiner/divider may include an isolation circuit including a first resonant circuit and a second resonant circuit coupled to terminals (e.g., input terminals, output terminals) of the power combiner/divider. The first resonant circuit may attenuate signals having frequencies in a first frequency range below an attenuation threshold between the terminals of the power combiner/divider. The second resonant circuit may attenuate signals having frequencies in a second frequency range below an attenuation threshold between the terminals of the power combiner/divider.

Abstract: This disclosure is directed to a power combiner/divider with improved operating frequency range (e.g., bandwidth) compared to other power combiners/dividers. The power combiner/divider may include an isolation circuit including a first resonant circuit and a second resonant circuit coupled to terminals (e.g., input terminals, output terminals) of the power combiner/divider. The first resonant circuit may attenuate signals having frequencies in a first frequency range below an attenuation threshold between the terminals of the power combiner/divider. The second resonant circuit may attenuate signals having frequencies in a second frequency range below an attenuation threshold between the terminals of the power combiner/divider.

Abstract: The present disclosure describes a circuit that includes a first inductor having a first terminal and second terminal, a second inductor having a third terminal and a fourth terminal, a first capacitor circuit, and a second capacitor circuit. The first and third terminals have a same polarity. The first capacitor circuit is cross-coupled to the first terminal and the fourth terminal. The second capacitor circuit is cross-coupled to the second terminal and the third terminal. The first and second capacitor circuits adjust an electrical coupling between the first and second inductor.

Abstract: In an aspect, an apparatus may be an apparatus for wireless communication. The apparatus for wireless communication may include a transceiver, a memory, and at least one processor coupled to the memory and configured to execute instructions stored in the memory to control the transceiver. In another aspect, an apparatus may be an apparatus for wireless communication. The apparatus for wireless communication may include a patch antenna coupled to the transceiver. The patch antenna includes a patch, a ground plane substantially located with respect to the patch, a probe feed coupled to the patch, and a slot-coupled feed configured to couple to the patch.

Abstract: An integrated circuit (IC) includes a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The capacitor array includes a pair of capacitor manifolds coupled to parallel capacitor routing traces and capacitors coupled between each pair of parallel capacitor routing traces. The IC also includes an inductor trace having at least one turn in at least one second BEOL interconnect level. The inductor trace defines a perimeter to overlap at least a portion of the capacitor array.

Abstract: An integrated circuit includes a capacitor (e.g., a folded metal-oxide-metal (MOM) capacitor) formed in the lower BEOL interconnect levels, without degrading an inductor's Q-factor. The integrated circuit includes the capacitor in one or more back-end-of-line (BEOL) interconnect levels. The capacitor includes multiple folded capacitor fingers having multiple sides and a pair of manifolds on a same side of the folded capacitor fingers. Each of the pair of manifolds is coupled to one or more of the folded capacitor fingers. The integrated circuit also includes an inductive trace having one or more turns in one or more different BEOL interconnect levels. The inductive trace overlaps one or more portions of the capacitor.

Abstract: Certain aspects of the present disclosure provide a directional coupler. In certain aspects, the directional coupler generally includes a first inductor and a second inductor wirelessly coupled to the first inductor. In certain aspects, the directional coupler generally includes an input port at a first terminal of the first inductor and a transmitted port at a second terminal of the first inductor. In certain aspects, the directional coupler generally includes a coupled port at a first terminal of the second inductor and an isolated port at a second terminal of the second inductor. In certain aspects, the directional coupler generally includes a first complex impedance component directly coupled to the isolated port and a second complex impedance component directly coupled to the coupled port.

Abstract: Certain aspects of the present disclosure are generally directed to a structure for a balanced-unbalanced (balun) transformer. For example, certain aspects of the present disclosure provide a transformer that generally includes a first winding having a first terminal coupled to an input node and a second terminal coupled to a reference potential node. The transformer may also include a first impedance coupled between a center tap of the first winding and the reference potential node, and a second winding magnetically coupled to the first winding and having a first terminal coupled to a first differential node of a differential output pair, a second terminal coupled to a second differential node of the differential output pair, and a center tap coupled to the reference potential node.

Abstract: Aspects generally relate to forming components in an area inside a guard ring structure in an integrated circuit.

Abstract: An integrated circuit with differential metal-oxide-metal (MOM)/metal-insulator-metal (MIM) capacitors to improve circuit isolation includes a first multi-layer capacitor in a first path of a differential circuit and a second multi-layer capacitor in a second path of the differential circuit. The first multi-layer capacitor resides in a first interconnect layer and a second interconnect layer and includes a first pair of ports. The second multi-layer capacitor overlaps one or more portions of the first multi-layer capacitor. The second multi-layer capacitor includes a second pair of ports and resides in a third interconnect layer and a fourth interconnect layer.

Abstract: Various aspects described herein relate to low-loss multi-band multiplexing schemes for a wireless communications system, for example, a 5th Generation (5G) New Radio (NR) system. In an aspect, a multiplexer for multi-band wireless communications comprises at least one tuning component configured to transmit or receive at least one signal within a frequency band that is selected from a plurality of frequency bands. The multiplexer further comprises at least one combining component, communicatively coupled with the at least one tuning component, configured to transmit or receive the at least one signal within the selected frequency band. In an aspect, the at least one tuning component is integrated on a chip and the at least one combining component is not integrated on the chip.

Abstract: Certain aspects of the present disclosure are generally directed to a structure for a balanced-unbalanced (balun) transformer. For example, certain aspects of the present disclosure provide a transformer that generally includes a first winding having a first terminal coupled to an input node and a second terminal coupled to a reference potential node. The transformer may also include a first impedance coupled between a center tap of the first winding and the reference potential node, and a second winding magnetically coupled to the first winding and having a first terminal coupled to a first differential node of a differential output pair, a second terminal coupled to a second differential node of the differential output pair, and a center tap coupled to the reference potential node.

Abstract: A coplanar waveguide may include a first transmission line extending between a first ground plane and a second ground plane at a first interconnect level. The coplanar waveguide may further include a shielding layer at a second interconnect level. The shielding layer may include a first set of conductive fingers coupled to the first ground plane. The first set of conductive fingers may be interdigitated with a second set of conductive fingers that are coupled to the second ground plane. Only a dielectric layer may be between the first set of conductive interdigitated fingers and the second set of conductive interdigitated fingers. The first ground plane, the second ground plane, the dielectric layer, and the shielding layer may form a capacitor.

Abstract: Certain aspects of the present disclosure provide techniques and apparatus employing an isolation ring having a center strip of conductive material used to isolate magnetic fields generated by common-mode and differential-mode current flow through one or more inductors disposed in the ring. The apparatus generally includes an electrical component having an inductive element and a ring of electrically conductive material encircling the inductive element, wherein the ring has a strip of electrically conductive material disposed in the ring and connecting a first point on the ring to a second point on the ring.

Abstract: An integrated circuit includes a capacitor (e.g., a folded metal-oxide-metal (MOM) capacitor) formed in the lower BEOL interconnect levels, without degrading an inductor's Q-factor. The integrated circuit includes the capacitor in one or more back-end-of-line (BEOL) interconnect levels. The capacitor includes multiple folded capacitor fingers having multiple sides and a pair of manifolds on a same side of the folded capacitor fingers. Each of the pair of manifolds is coupled to one or more of the folded capacitor fingers. The integrated circuit also includes an inductive trace having one or more turns in one or more different BEOL interconnect levels. The inductive trace overlaps one or more portions of the capacitor.

Abstract: An integrated circuit (IC) includes a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The capacitor array includes a pair of capacitor manifolds coupled to parallel capacitor routing traces and capacitors coupled between each pair of parallel capacitor routing traces. The IC also includes an inductor trace having at least one turn in at least one second BEOL interconnect level. The inductor trace defines a perimeter to overlap at least a portion of the capacitor array.

Abstract: A capacitor radio frequency (RF) shielding structure may include a ground plane partially surrounding a coupling capacitor in an RF signal path. The ground plane may include a first ground plane portion extending between a positive terminal of the RF signal path and a negative terminal of the RF signal path. The ground plane may include a second ground plane portion extending between the positive terminal and the negative terminal of the RF signal path. The second ground plane portion may be opposed the first ground plane portion. The capacitor RF shielding structure may also include a patterned shielding layer electrically contacting the first ground plane portion and/or the second ground plane portion. The patterned shielding layer may electrically disconnecting a return current path over the patterned shielding layer to confine a return current to flowing over the first ground plane portion or the second ground plane portion.

Abstract: A coplanar waveguide may include a first transmission line extending between a first ground plane and a second ground plane at a first interconnect level. The coplanar waveguide may further include a shielding layer at a second interconnect level. The shielding layer may include a first set of conductive fingers coupled to the first ground plane. The first set of conductive fingers may be interdigitated with a second set of conductive fingers that are coupled to the second ground plane. Only a dielectric layer may be between the first set of conductive interdigitated fingers and the second set of conductive interdigitated fingers. The first ground plane, the second ground plane, the dielectric layer, and the shielding layer may form a capacitor.