Abstract: A photoelectric computing unit, a photoelectric computing array and a photoelectric computing method. The photoelectric computing unit includes a semiconductor multifunctional region structure, which includes at least one carrier control region, at least one coupling region, and at least one photon-generated carrier collection region and readout region.

Abstract: A photoelectric computing unit, a photoelectric computing array and a photoelectric computing method. The photoelectric computing unit includes a semiconductor multifunctional region structure, which includes at least one carrier control region, at least one coupling region, and at least one photon-generated carrier collection region and readout region.

Abstract: A two-by-two array consists of four pixels. Each pixel comprises one light-sensing transistor and one reading transistor. Both the light sensing transistor and the reading transistor are formed above a same P-type semiconductor substrate, and have a composite dielectric gate structure. The substrates of the four reading transistors are connected to form a regular octagonal ring structure located in the center of the array. On four sides of the regular octagonal ring structure, four heavily-doped N+ regions are formed on the substrates not covered with the composite dielectric gate, of which every two regions are opposite to each other and form right angles, wherein two opposite heavily-doped N+ regions are connected to form a shared N+ source, and the other two are connected to form a shared N+ drain.

Abstract: A two-by-two array consists of four pixels. Each pixel comprises one light-sensing transistor and one reading transistor. Both the light sensing transistor and the reading transistor are formed above a same P-type semiconductor substrate, and have a composite dielectric gate structure. The substrates of the four reading transistors are connected to form a regular octagonal ring structure located in the center of the array. On four sides of the regular octagonal ring structure, four heavily-doped N+ regions are formed on the substrates not covered with the composite dielectric gate, of which every two regions are opposite to each other and form right angles, wherein two opposite heavily-doped N+ regions are connected to form a shared N+ source, and the other two are connected to form a shared N+ drain.