Abstract: Methods and systems for generating a floorplan for a circuit are disclosed. A netlist graph of the circuit and block features associated with blocks of the circuit are obtained. A reinforcement learning (RL) agent is used to generate a sequence of corner block list (CBL) actions. Each CBL action is generated by: generating a current state embedding representing a current state of the floorplan; and inputting the current state embedding to a policy network of the RL agent to generate a predicted output vector, which is used to generate the CBL action. After each CBL action is generated, the current CBL representation of the floorplan and the block features are updated to reflect the state of the floorplan after applying the CBL action. The CBL representation is outputted as a final floorplan after all blocks have been placed.

Abstract: Method and system for assisting electronic chip design, comprising: receiving netlist data for a proposed electronic chip design, the netlist data including a list of circuit elements and a list of interconnections between the circuit elements; converting the netlist data to a graph that represents at least some of the circuit elements as nodes and represents the interconnections between the circuit elements as edges; extracting network embeddings for the nodes based on a graph topology represented by the edges; extracting degree features for the nodes based on the graph topology; and computing, using a graph neural network, a congestion prediction for the circuit elements that are represented as nodes based on the extracted network embeddings and the extracted degree features.

Abstract: Method and system for assisting electronic chip design, comprising: receiving netlist data for a proposed electronic chip design, the netlist data including a list of circuit elements and a list of interconnections between the circuit elements; converting the netlist data to a graph that represents at least some of the circuit elements as nodes and represents the interconnections between the circuit elements as edges; extracting network embeddings for the nodes based on a graph topology represented by the edges; extracting degree features for the nodes based on the graph topology; and computing, using a graph neural network, a congestion prediction for the circuit elements that are represented as nodes based on the extracted network embeddings and the extracted degree features.

Abstract: A microfluidic injection and manifold assembly includes a microfluidic chip having at least a first fluid port and a second fluid port, and a fluid pathway between the first fluid port and the second fluid port. A manifold has a seat on which the microfluidic chip is received, and at least a first fluid channel. The fluid channel has an external fluid port spaced from the seat and an internal fluid port in the seat and connected in fluid communication with the first fluid port of the microfluidic chip. At least a first injector is secured to the manifold and has a plunger and a drive assembly. The drive assembly is activatable to force the plunger into the external fluid port of the manifold to force fluid from the first fluid channel of the manifold into the fluid pathway of the microfluidic chip.

Abstract: A microfluidic injection and manifold assembly includes a microfluidic chip having at least a first fluid port and a second fluid port, and a fluid pathway between the first fluid port and the second fluid port. A manifold has a seat on which the microfluidic chip is received, and at least a first fluid channel. The fluid channel has an external fluid port spaced from the seat and an internal fluid port in the seat and connected in fluid communication with the first fluid port of the microfluidic chip. At least a first injector is secured to the manifold and has a plunger and a drive assembly. The drive assembly is activatable to force the plunger into the external fluid port of the manifold to force fluid from the first fluid channel of the manifold into the fluid pathway of the microfluidic chip.