Patents by Inventor Zhangxi Tan

Zhangxi Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230362247
    Abstract: A storage system is provided. The storage system includes a plurality of storage nodes, each of the plurality of storage nodes having a plurality of storage units with storage memory. The system includes a first network coupling the plurality of storage nodes and a second network coupled to at least a subset of the plurality of storage units of each of the plurality of storage nodes such that one of the plurality of storage units of a first one of the plurality of storage nodes can initiate or relay a command to one of the plurality of storage units of a second one of the plurality of storage nodes via the second network without the command passing through the first network.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 9, 2023
    Inventors: PAR BOTES, JOHN HAYES, ZHANGXI TAN
  • Publication number: 20230267040
    Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 24, 2023
    Inventors: JOHN D. DAVIS, JOHN HAYES, HARI KANNAN, NENAD MILADINOVIC, ZHANGXI TAN
  • Publication number: 20230251944
    Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.
    Type: Application
    Filed: April 3, 2023
    Publication date: August 10, 2023
    Inventors: JOHN D. DAVIS, JOHN HAYES, HARI KANNAN, NENAD MILADINOVIC, ZHANGXI TAN
  • Patent number: 11722567
    Abstract: A storage system is provided. The storage system includes a plurality of storage nodes, each of the plurality of storage nodes having a plurality of storage units with storage memory. The system includes a first network coupling the plurality of storage nodes and a second network coupled to at least a subset of the plurality of storage units of each of the plurality of storage nodes such that one of the plurality of storage units of a first one of the plurality of storage nodes can initiate or relay a command to one of the plurality of storage units of a second one of the plurality of storage nodes via the second network without the command passing through the first network.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: August 8, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Par Botes, John Hayes, Zhangxi Tan
  • Patent number: 11656939
    Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: May 23, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
  • Patent number: 11620197
    Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: April 4, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
  • Publication number: 20230089583
    Abstract: A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.
    Type: Application
    Filed: November 18, 2022
    Publication date: March 23, 2023
    Inventors: John D. Davis, John Hayes, Zhangxi Tan, Hari Kannan, Nenad Miladinovic
  • Patent number: 11544143
    Abstract: A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 3, 2023
    Assignee: Pure Storage, Inc.
    Inventors: John D. Davis, John Hayes, Zhangxi Tan, Hari Kannan, Nenad Miladinovic
  • Publication number: 20220404970
    Abstract: A storage system is provided. The storage system includes a plurality of non-volatile memory units and a processor operatively coupled to a plurality of non-volatile memory units. The processor is to perform a method including receiving a request to read data from the storage system. The method also includes determining whether a storage operation should be delayed, based on the request to read the data from the storage system. The method further includes in response to determining that the storage operation should be delayed, delaying the storage operation. The method further includes performing a read operation for the request to read the data.
    Type: Application
    Filed: August 26, 2022
    Publication date: December 22, 2022
    Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
  • Patent number: 11442625
    Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: September 13, 2022
    Assignee: Pure Storage, Inc.
    Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
  • Patent number: 11392522
    Abstract: A method of applying a data format in a direct memory access transfer is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a single chassis that couples the storage nodes as a cluster, each of the plurality of storage nodes having nonvolatile solid-state memory for user data storage. The method includes reading a self-describing data portion from a first memory of the nonvolatile solid-state memory and extracting a destination from the self-describing data portion. The method includes writing data, from the self-describing data portion, to a second memory of the nonvolatile solid-state memory according to the destination.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: July 19, 2022
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, Shantanu Gupta, John Davis, Brian Gold, Zhangxi Tan
  • Publication number: 20220103632
    Abstract: A storage system is provided. The storage system includes a plurality of storage nodes, each of the plurality of storage nodes having a plurality of storage units with storage memory. The system includes a first network coupling the plurality of storage nodes and a second network coupled to at least a subset of the plurality of storage units of each of the plurality of storage nodes such that one of the plurality of storage units of a first one of the plurality of storage nodes can initiate or relay a command to one of the plurality of storage units of a second one of the plurality of storage nodes via the second network without the command passing through the first network.
    Type: Application
    Filed: December 10, 2021
    Publication date: March 31, 2022
    Inventors: Par Botes, John Hayes, Zhangxi Tan
  • Publication number: 20220083420
    Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.
    Type: Application
    Filed: November 24, 2021
    Publication date: March 17, 2022
    Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
  • Patent number: 11240307
    Abstract: A storage system is provided. The storage system includes a plurality of storage nodes, each of the plurality of storage nodes having a plurality of storage units with storage memory. The system includes a first network coupling the plurality of storage nodes and a second network coupled to at least a subset of the plurality of storage units of each of the plurality of storage nodes such that one of the plurality of storage units of a first one of the plurality of storage nodes can initiate or relay a command to one of the plurality of storage units of a second one of the plurality of storage nodes via the second network without the command passing through the first network.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 1, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Par Botes, John Hayes, Zhangxi Tan
  • Patent number: 11204830
    Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: December 21, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
  • Publication number: 20210365337
    Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 25, 2021
    Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
  • Patent number: 11080154
    Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 3, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
  • Patent number: 11079962
    Abstract: A non-volatile solid-state storage is provided. The non-volatile solid state storage includes a non-volatile random access memory (NVRAM) addressable by a processor external to the non-volatile solid state storage. The NVRAM is configured to store user data and metadata relating to the user data. The non-volatile solid state storage includes a flash memory addressable by the processor. The flash memory is configured to store the user data responsive to the processor directing transfer of the user data from the NVRAM to the flash memory.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 3, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John Davis, John Hayes, Brian Gold, Shantanu Gupta, Zhangxi Tan
  • Publication number: 20210216398
    Abstract: A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Inventors: John D. Davis, John Hayes, Zhangxi Tan, Hari Kannan, Nenad Miladinovic
  • Publication number: 20210216209
    Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan