Abstract: The disclosure provides a manufacturing method for a fin field-effect transistor. The method to make the fin field-effect transistor comprises: forming a fin structure and a gate structure spanning on the fin structure on a substrate; and forming a source-drain region on the fin structure, which comprises: forming an epitaxial layer; and forming a sacrificial layer on the surface of the epitaxial layer to prevent the epitaxial layer from being lost in the subsequent removal steps.

Abstract: An epitaxial growth process for a semiconductor device includes providing a semiconductor substrate, forming a plurality of Dummy Gate structures on the surface of the semiconductor substrate, and forming grooves in a self-aligned manner on both sides of the Dummy Gate structures; forming an initial seed layer on the inner side surfaces of the grooves, the thickness of the formed initial seed layer on the bottoms of the grooves being greater and the thickness of the formed initial seed layer on the sidewalls being smaller since the growth speed of crystal faces <100> and <110> is different; longitudinally etching the initial seed layer to thin the bottom of the initial seed layer to form a seed layer; forming a main body layer on the seed layer, the main body layer filling the grooves; and forming a cover layer on the main body layer.

Abstract: Provided is a method for manufacturing a 14 nm-node BEOL 32 nm-width metal. A semiconductor structure for manufacturing BEOL wire is provided, wherein the semiconductor structure at least comprises a carbon coating and intermediate layer on it; forming a photoresist layer on the intermediate layer and exposing the photoresist layer according to a layout; developing the exposed photoresist layer by using a developing solution, and causing the developed photoresist to react with the intermediate layer in a contact region of the developed photoresist to form a peg groove; and etching by using the groove in the semiconductor structure to form a 14 nm-node BEOL 32 nm-width metal. This application can reducing the longitudinal shrink of the metal wire, achieving the improvement of the lateral and longitudinal shrink uniformity, reducing defects caused by misalignment of the through hole and the metal wire, and increasing the effective usable area of a chip.

Abstract: The present disclosure relates to a FinFET and a manufacturing method of a contact. The manufacturing method comprises steps of: sequentially generating an interlayer dielectric layer, a metal hard mask, an oxide protective cap and a tri-layer mask on a gate to form a device to be etched; photoetching the tri-layer mask to remove photoresist in a non-patterned area; performing main etch on the device to be etched after the photoetching to remove the interlayer dielectric layer in the area that is not covered by the metal hard mask, and the metal hard mask is provided with the oxide protective cap; performing ODL removal on the device to be etched after the main etch to remove remaining part of the tri-layer mask; performing oxide etch on the device to be etched after the ODL removal to remove the oxide protective cap; and generating the contact on the device after the oxide etch. The present disclosure can accurately control the critical dimensions of the contact in an X direction and a Y direction.

Abstract: The present application discloses a method for forming a recess, which comprises the following steps: step 1: performing a dry etching process to a silicon substrate to form a U-shaped or ball-shaped recess; step 2: performing second etching to the recess by introducing HCl and GeH4 reaction gases in an epitaxial process chamber to form diamond-shaped recess. The present application further discloses a method for forming a recess and filling the recess with an epitaxial layer in situ. The disclosed etching changes U-shaped or ball-shaped reaction recess diamond-shaped recess by including reaction gases in the epitaxial process chamber, which is conducive to realizing the in-situ epitaxial filling process. This method reduces steps in the process loop of forming embedded epitaxial layer, thus decreasing defects from the process.

Abstract: An epitaxial growth process for a semiconductor device includes providing a semiconductor substrate, forming a plurality of Dummy Gate structures on the surface of the semiconductor substrate, and forming grooves in a self-aligned manner on both sides of the Dummy Gate structures; forming an initial seed layer on the inner side surfaces of the grooves, the thickness of the formed initial seed layer on the bottoms of the grooves being greater and the thickness of the formed initial seed layer on the sidewalls being smaller since the growth speed of crystal faces <100> and <110> is different; longitudinally etching the initial seed layer to thin the bottom of the initial seed layer to form a seed layer; forming a main body layer on the seed layer, the main body layer filling the grooves; and forming a cover layer on the main body layer.

Abstract: The disclosure provides a manufacturing method for a fin field-effect transistor. The method to make the fin field-effect transistor comprises: forming a fin structure and a gate structure spanning on the fin structure on a substrate; and forming a source-drain region on the fin structure, which comprises: forming an epitaxial layer; and forming a sacrificial layer on the surface of the epitaxial layer to prevent the epitaxial layer from being lost in the subsequent removal steps.

Abstract: The present disclosure relates to a FinFET and a manufacturing method of a contact. The manufacturing method comprises steps of: sequentially generating an interlayer dielectric layer, a metal hard mask, an oxide protective cap and a tri-layer mask on a gate to form a device to be etched; photoetching the tri-layer mask to remove photoresist in a non-patterned area; performing main etch on the device to be etched after the photoetching to remove the interlayer dielectric layer in the area that is not covered by the metal hard mask, and the metal hard mask is provided with the oxide protective cap; performing ODL removal on the device to be etched after the main etch to remove remaining part of the tri-layer mask; performing oxide etch on the device to be etched after the ODL removal to remove the oxide protective cap; and generating the contact on the device after the oxide etch. The present disclosure can accurately control the critical dimensions of the contact in an X direction and a Y direction.

Abstract: Provided is a method for manufacturing a 14 nm-node BEOL 32 nm-width metal. A semiconductor structure for manufacturing BEOL wire is provided, wherein the semiconductor structure at least comprises a carbon coating and intermediate layer on it; forming a photoresist layer on the intermediate layer and exposing the photoresist layer according to a layout; developing the exposed photoresist layer by using a developing solution, and causing the developed photoresist to react with the intermediate layer in a contact region of the developed photoresist to form a peg groove; and etching by using the groove in the semiconductor structure to form a 14 nm-node BEOL 32 nm-width metal. This application can reducing the longitudinal shrink of the metal wire, achieving the improvement of the lateral and longitudinal shrink uniformity, reducing defects caused by misalignment of the through hole and the metal wire, and increasing the effective usable area of a chip.

Abstract: The present disclosure provides a transistor gate structure and a manufacturing method for the transistor gate structure. The transistor gate structure is located on a substrate, the gate structure being isolated from the substrate by a gate insulating layer, and the gate structure comprises a work function layer and a plurality of sets of composite barrier layers located between the work function layer and the gate insulating layer, and each set of the plurality of sets of composite barrier layers comprise laminated first and second barrier layers, the material of the first barrier layer being different from that of the second barrier layer. By forming a plurality of sets of alternately laminated first and second barrier layers, a superior barrier effect can be achieved and the stability of the electric characteristics of a device can be improved.

Abstract: A manufacture method of high-efficiency non-oriented silicon steel with excellent magnetic property includes the steps of smelting a chemical composition of non-oriented silicon steel, by weight percent, is: C?0.0040%, Si:0.1˜0.8%, Al:0.002˜1.0%, Mn:0.10˜1.50%, P:?0.2%, Sb:0.04˜0.08%, S?0.0030%, N?0.0020%, Ti?0.0020%, and the rest is Fe and unavoidable inclusions. The molten steel is then cast into billets which are hot-rolled into a hot-rolled product. The heating temperature for the billet is 1100°˜1150° and the finish-rolling temperature is 860°˜920°. The hot-rolled product is then air cooled for a period of time within a range determined by air cooling time t: (2+30xSb %)s?t?7 s. The hot-rolled product is reeled at a temperature ?720° and cold-rolled to form cold-rolled plate with a target thickness at a reduction ratio of 70˜78% followed by heating up the cold-rolled plate to 800˜1000° at heating rate of ?15°/s, and holding time of 10 s˜25 s.

Abstract: A manufacture method of high-efficiency non-oriented silicon steel with excellent magnetic property, which comprises the following steps: 1) smelting and casting; chemical compositions of non-oriented silicon steel, by weight percent, are: C?0.0040%, Si: 0.1˜0.8%, Al: 0.002˜1.0%, Mn: 0.10˜1.50%, P: ?0.2%, Sb: 0.04˜0.08%, S?0.0030%, N?0.0020%, Ti?0.0020%, and the rest is Fe and unavoidable inclusions; molten steel in accordance with the above compositions is smelted and then casted into billets; 2) hot-rolling and pickling; heating temperature for slab is 1100° C.˜1150° C. and finish-rolling temperature is 860° C.˜920° C.; after rolling, the hot-rolled product is air cooled, during which air cooling time t: (2+30×Sb %)s?t?7 s; thereafter reeling at a temperature ?720° C. ; 3) cold-rolling; rolling to form cold-rolled plate with target thickness at a reduction ratio of 70˜18%; 4) annealing; heating up the cold-rolled plate to 800˜1000° C. at heating rate of ?15° C./s, and holding time is 10 s˜25 s.

Abstract: A cold rolled electromagnetic steel sheet for rapid cycling synchrotron, and a manufacturing method thereof, the method includes the steps of 1) smelting and casting, the composition of the cold rolled electromagnetic steel sheet is C 0.001-0.003 wt %, Si 0.60%-0.90 wt %, Mn 0.40%-0.70 wt %, P?0.04 wt %, Al 0.60-0.80 wt %, S?0.0035 wt %, N?0.003 wt %, and the rest is Fe; smelting and RH refining, and then casting to form semi-finished product; 2) hot rolling; 3) normalizing, in which the normalizing temperature is controlled between 960° C.-980° C., and the normalizing time is 30-60 sec; 4) pickling and cold rolling; 5) annealing, wherein the annealing temperature is controlled to be between 850° C.-870° C., and the annealing time is 13-15 sec; 6) obtaining non-oriented silicon steel product after coating.

Abstract: A non-oriented electrical steel has relative high magnetic induction and high intensity without increasing manufacturing difficulty. The weight percentage of the compositions of the electrical steel are as follows: C?0.0040%, Si is 2.50% to 4.00%, Al is 0.20% to 0.80%, Cr is 1.0 to 8.0%, Ni is 0.5 to 5.0%, Mn?0.50%, P?0.30%, S?0.0020%, N?0.0030%, Ti?0.0030%, Nb?0.010%, V?0.010%, C+S+N+Ti?0.010%, and a balance substantially being Fe and inevitable impurities.

Abstract: A manufacture process of non-oriented silicon steel with high magnetic induction includes smelting and casting steel having a chemical composition by weight percent: Si 0.1˜1%, Al 0.005˜1.0%, C?0.004%, Mn=0.10˜1.50%, P?0.2%, S?0.005%, N?0.002, Nb+V+Ti?0.006%, and the rest is Fe. The steel is cast into a billet, which is heated and hot-rolled to 1150˜1200° C. into a plate at a finish-rolling temperature 830˜900° C. The plate is cooled to a temperature ?570° C. and cold-roll flattened at compression ratio 2˜5%. The flattened plate is normalized at temperature not below 950° C. for 30˜180s, and then pickled and cold-rolled into a sheet with thickness of the finished product. The sheet is finish-annealed quickly heating the sheet to 800˜1000° C. at temperature rise rate ?100° C./s, soaking the heated sheet for 5˜60s at the temperature, and then slowly cooling the sheet to 600˜750° C.