Abstract: The present disclosure relates to a dual-function protein for regulating blood glucose and lipid metabolism, wherein said dual-function protein comprises a human GLP-1 analog and human FGF21. In the present disclosure, provided is a method for preparing said dual function protein, and also provided is the use of said dual-function protein in the preparation of a biological substance for treating type 2 diabetes, obesity, dyslipidemia, fatty liver disease and/or metabolic syndrome. The dual-function protein provided in the present disclosure can synergistically regulate blood glucose and lipid levels in vivo, and satisfy multiple requirements for patients with type 2 diabetes such as lowering blood glucose, relieving hepatic steatosis, reducing body weight and improving metabolic disorders of circulating lipids.

Abstract: A well cementing method is described for improving cementing quality by controlling the hydration heat of cement slurry. By controlling the degree and/or rate of hydration heat release from cement slurry, the method improves the hydration heat release during formation of cement with curing of cement slurry, improves the binding quality between the cement and the interfaces, and in turn improves the cementing quality at the open hole section and/or the overlap section. The cementing method improves cementing quality of oil and gas wells and reduces the risk of annular pressure.

Abstract: A semiconductor chip includes a substrate and a semiconductor layer positioned above the substrate. A hybrid through-silicon via (“TSV”) extends continuously through at least the semiconductor layer and the substrate and includes a first TSV portion and a second TSV portion. A lower portion of the first TSV portion is positioned in the substrate and has a lower surface adjacent to a back side of the substrate and an upper surface below the semiconductor layer. Upper sidewall portions of the first TSV portion extend from the upper surface through at least the semiconductor layer. A depth of the lower portion is greater than a thickness of the upper sidewall portions. The second TSV portion is conductively coupled to the first TSV portion, is laterally surrounded by the upper sidewall portions, and extends continuously from the upper surface through at least the semiconductor layer.

Abstract: A semiconductor chip includes a substrate and a semiconductor layer positioned above the substrate. A hybrid through-silicon via (“TSV”) extends continuously through at least the semiconductor layer and the substrate and includes a first TSV portion and a second TSV portion. A bottom plug portion of the first TSV portion is positioned in the substrate and has a lower surface adjacent to a back side of the substrate and an upper surface below the semiconductor layer. Upper sidewall portions of the first TSV portion extend from the upper surface through at least the semiconductor layer. A depth of the bottom plug portion is greater than a thickness of the upper sidewall portions. The second TSV portion is conductively coupled to the first TSV portion, is laterally surrounded by the upper sidewall portions, and extends continuously from the upper surface through at least the semiconductor layer.

Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.

Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process.

Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process.

Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.

Abstract: In an embodiment of the present invention, a call request is received from a calling party. A ring tone is selectively provided to the calling party based on at least one of a calling party identifier and a time parameter. In another embodiment of the present invention, a call request is received from a calling party. A message including a video element is selectively provided based on at least one of a calling party identifier and a time parameter.

Abstract: A radio frequency front-end receiver includes a single stage low noise amplifier connected with a resistor array and a capacitor array, and a Gilbert-type mixer connected with a PMOS transconductance stage, an inductor and a serially connected current source. The resistor array enables the adjustment of the power gain of the low noise amplifier. The capacitor array tunes the low noise amplifier so that the maximum power gain is at the desired operating frequency. The PMOS transconductance stage reduces the power consumption of the mixer. The inductor increases the impedance and the current source improves the common-mode rejection of the mixer.

Abstract: A radio frequency front-end receiver includes a single stage low noise amplifier connected with a resistor array and a capacitor array, and a Gilbert-type mixer connected with a PMOS transconductance stage, an inductor and a serially connected current source. The resistor array enables the adjustment of the power gain of the low noise amplifier. The capacitor array tunes the low noise amplifier so that the maximum power gain is at the desired operating frequency. The PMOS transconductance stage reduces the power consumption of the mixer. The inductor increases the impedance and the current source improves the common-mode rejection of the mixer.