Abstract: A gene chip includes a chip carrier, a plurality of DNA nanoballs assembled on the chip carrier, and a polymer film formed on the chip carrier and wrapping the DNA nanoballs. The polymer film includes at least one of a film of a positively charged polymer, a film of a positively charged polymer which is modified, a film of a zwitterionic polymer, and a composite polymer film. The composite polymer film is formed by a layer-by-layer self-assembly process of a positively charged polymer and a negatively charged polymer. The gene chip has good sequencing quality and different functions can be achieved by coating with different polymers, such as the chip surface rapidly drying out and surface non-specific adsorption. A method of preparing a gene chip is further disclosed.

Abstract: The disclosed device includes multiple special purpose processors that are configured to perform, in parallel, a power on transition sequence for the device, which can involve restoring a data state of components of the device using data stored in local storages of the special purpose processors. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: In an example, a memory device includes a first stack structure and a second stack structure over the first stack structure. Each of the first stack structure and the second stack structure includes alternately stacked conductor layers and first insulating layers. The memory device also includes a first channel structure extending through the first stack structure, and a second channel structure extending through the second stack structure and connected with the first channel structure. A width of an end of the first channel structure closer to the second channel structure is greater than that of the second channel structure closer to the first channel structure. The memory device further includes a pillar structure extending through the first stack structure and the second stack structure. The pillar structure includes a metal layer.

Abstract: In an embodiment of the disclosure, disclosed is a circuit based on in-memory computing in a digital domain, including: an array of computational storage cells, the computational storage cells including a preset number of data storage cells and a preset number of single-bit multipliers in one-to-one correspondence; an adder tree configured to accumulate products output by respective computational storage cells to obtain an accumulated result; and a multi-bit input transfer logic configured to convert accumulated results output by the adder tree and corresponding to respective single bits included in the input feature data into a multiply-accumulate result of multi-bit input feature data and multi-bit weight data. An in-memory multiply-accumulation is implemented or multi-bit weight data and input feature data, so that efficiency and energy efficiency density of in-memory computing is improved, “read disturb write” issue caused by a voltage change on bit lines is avoided, and computing stability is improved.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.

Abstract: Disclosed is an apparatus for charging a battery comprising a first charging device configured to communicate with at least one second charging device, the first charging device and the at least one second charging device configured to charge the battery, and comprising a first controller configured to control the first charging device, wherein the first controller determines the number of the at least one second charging devices by communicating with a second controller.

Abstract: A circuit with a pseudo class-AB structure is shown. The circuit has an output stage, a first capacitor, and a first impedance component. The output stage has a first PMOS (p-type Metal-Oxide-Semiconductor Field-Effect Transistor) and a first NMOS (n-type MOSFET). The first connection node between the drain terminal of the first PMOS and the drain terminal of the first NMOS is coupled to the first output terminal of the circuit. The first capacitor is coupled between the gate terminal of the first PMOS and the gate terminal of the first NMOS. The first impedance component is coupled in parallel with the first capacitor between the gate terminal of the first PMOS and the gate terminal of the first NMOS.

Abstract: Disclosed is an apparatus for charging a battery comprising a first charging device configured to communicate with at least one second charging device, the first charging device and the at least one second charging device configured to charge the battery, and comprising a first controller configured to control the first charging device, wherein the first controller determines the number of the at least one second charging devices by communicating with a second controller.

Abstract: A vacuum cleaner that includes a surface cleaning head including a dirty air inlet, a brush supported by the surface cleaning head, a motor coupled to and operable to cause movement of the brush, a sensor to sense a voltage associated with a current of the motor, and a controller configured to control an amount of current provided to the motor in response to the sensed voltage. The controller is configured to control a first pulse width modulated (PWM) duty cycle provided to the motor when the sensed voltage is less than a reference voltage, control a second PWM duty cycle provided to the motor when the sensed voltage is greater than the reference voltage, the second PWM duty cycle being less than the first PWM duty cycle, and turn off the motor when the sensed voltage increases to a voltage associated with an overload current of the motor.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: A vacuum cleaner having a surface cleaning head and a brush supported by the surface cleaning head. A control circuit operates the vacuum cleaner. The control circuit includes a motor coupled to and operable to cause movement of the brush. Also disclosed is a method of controlling a motor for a brush of a vacuum cleaner. The method includes sensing an electrical parameter related to an amount of carpet load restricting the brush and determining a pulse width modulated duty cycle value based on the electrical parameter.

Abstract: An information handling system includes power inputs, a battery, a BMC, a memory, and a processor. The BMC determines which of the power inputs are coupled to associated power sources, and a first duration of time that the battery can provide power to the information handling system. The memory stores a firmware element. The processor receives a firmware that includes a second indication as to which of the power inputs are to be coupled to their associated power source as a condition for saving the firmware update, and that includes a second duration of time that it is expected to take to save the firmware update. The information handling system saves the firmware update to the memory when the first indication matches the second indication and when the first duration of time is greater than the second duration of time.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: An information handling system includes power inputs, a battery, a BMC, a memory, and a processor. The BMC determines which of the power inputs are coupled to associated power sources, and a first duration of time that the battery can provide power to the information handling system. The memory stores a firmware element. The processor receives a firmware that includes a second indication as to which of the power inputs are to be coupled to their associated power source as a condition for saving the firmware update, and that includes a second duration of time that it is expected to take to save the firmware update. The information handling system saves the firmware update to the memory when the first indication matches the second indication and when the first duration of time is greater than the second duration of time.

Abstract: A customized oral irrigator which is adapted to the user's dentition, has multiple nozzles or cutout openings to point to the area to irrigate. User can anchor such device by biting with the teeth and irrigate the teeth and gum, especially between the teeth and under the gum, in one instance. Such a device is fast and effective. It will be beneficial to everyone but will especially benefit busy professionals, children, seniors, handicapped, disabled, and other users who have difficulty cleaning teeth, for example people who wear dental devices such as braces. This device is meant to combine oral care procedures such as tooth brushing and dental flossing in one instance and will yield better dental hygiene and with better compliance than conventional brushing and flossing and conventional single channel oral irrigators.