Abstract: This application relates to the field of memory technology, in particular to a method and a system for remapping a row address on a multichannel DIMM. The method is applied to a memory controller, comprising: receiving a first read/write access address and extracting a first channel row address from the first read/write access address; encrypting and mapping the first channel row address through a key-based mapping method to obtain a second channel row address that corresponds to the first channel row address within a predetermined address range; forming a second read/write access address based on the second channel row address and unextracted address information in the first read/write access address, and performing read/write access to the DIMM based on the second read/write access address. The present application can alleviate side channel attack without causing degradation of read/write performance.

Abstract: A data security method and data security system configured to applied to a memory controller are provided. The data security method comprises: receiving a data writing request, wherein the data writing request comprises data to be written to a storage module and a storage address of the data; acquiring verification information of the data; and writing the data into the storage address, and writing the verification information into a redundant ECC bit corresponding to the data. The data security method and data security system according to the present disclosure can achieve the secure storage and reading of the data without extra space overhead, while maintaining high bandwidth and throughput.

Abstract: The present disclosure provides systems and methods for deriving a key from a basekey built-in a chip is provided. In an exemplary embodiment, there is provided a method for deriving a key from basekey built-in a chip that may comprise obtaining a basekey built-in the chip and a current version number when the chip starts up and runs read-only boot code, and performing iterations on the basekey via a one-way function to obtain a derived key of the current version. The number of times of the iterations is equal to the difference between a maximum version number and the current version number.

Abstract: A data compression method includes: storing data to be written into a first address and a second address into a data buffer in response to a data write request to the first address and the second address of a memory module from a host; according to a relationship between the first address and the second address, selecting a compression scheme from pre-configured compression schemes, and attempting to compress the data to be written into the first address and the second address into compressed data that can be stored into either the first address or the second address by using a pre-defined compression method, if the attempt to compress successes, storing the compressed data into the first address or the second address of the memory module, and identifying the compressed data by using redundant ECC bits to form first identification information.

Abstract: The application discloses a data encryption and decryption system and method. The system includes a host system, a sequencer, a hardware processor, multiple direct memory access modules, and multiple cryptography engines, the cryptography engine comprises an input buffer, an output buffer, a symmetric encryption/decryption algorithm module and a digest algorithm module. The host system determines encryption/decryption calculation method and/or digest calculation method, and generates corresponding encryption/decryption calculation commands and/or digest calculation commands. The sequencer analyzes the encryption/decryption calculation commands and/or digest calculation command to generate control flow commands, and controls one or more of the multiple direct memory access modules via the control flow commands to input data to be encrypted/decrypted into the input buffer of one or more cryptography engines.

Abstract: A task processing apparatus and a task processing method are provided. The task processing apparatus is coupled to a host apparatus, and includes: a controller configured to query whether there is a data processing task to be executed and trigger execution of the data processing task; at least one data processing engine configured to process operation data corresponding to the data processing task according to a configured working mode, and generate a data processing result; and at least one scheduler configured to: receive a task descriptor of the data processing task from the host apparatus; configure the working mode of the data processing engine based on the task descriptor; control transmission of the operation data corresponding to the data processing task from the host apparatus to the data processing engine; and control transmission of the data processing result from the data processing engine to the host apparatus.

Abstract: The present disclosure provides systems and methods for deriving a key from a basekey built-in a chip is provided. In an exemplary embodiment, there is provided a method for deriving a key from basekey built-in a chip that may comprise obtaining a basekey built-in the chip and a current version number when the chip starts up and runs read-only boot code, and performing iterations on the basekey via a one-way function to obtain a derived key of the current version. The number of times of the iterations is equal to the difference between a maximum version number and the current version number.

Abstract: A method to provide effective control and data flow information in an Intermediate Representation (IR) form. A Path Sensitive single Assignment (PSA) IR form with effective and explicit control and data path information supports control flow sensitive optimizations such as path sensitive symbolic substitution, array privatization and speculative multi threading. In the definition of PSA form, besides defining new versioned variables, the gamma functions keep control path information. The gamma function in PSA form keeps the basic attribute of SSA IR form and only one definition exists for each use. Therefore, all existing Single Static Assignment (SSA) IR form based analysis can be applied in PSA form. The gamma function in PSA form keeps all essential control flow information and eliminates unnecessary predicates at the same time.

Abstract: A method including providing a stream of content to a processor, transforming kernels within the stream of content through affine modeling, transforming the affine modeled kernels, stream contracting kernel processes, and stream blocking the kernel processes.

Abstract: A method for statement shifting to increase the parallelism of loops includes constructing a data dependence graph (DDG) to represent dependences between statements in a loop, constructing a basic equations group from the DDG, constructing a dependence equations group derived in part from the basic equations group, and determining a shifting vector for the loop from the dependence equations group, wherein the shifting vector to represent an offset to apply to each statement in the loop for statement shifting. Other embodiments are also disclosed.

Abstract: A method to provide effective control and data flow information in an Intermediate Representation (IR) form. A Path Sensitive single Assignment (PSA) IR form with effective and explicit control and data path information supports control flow sensitive optimizations such as path sensitive symbolic substitution, array privatization and speculative multi threading. In the definition of PSA form, besides defining new versioned variables, the gamma functions keep control path information. The gamma function in PSA form keeps the basic attribute of SSA IR form and only one definition exists for each use. Therefore, all existing Single Static Assignment (SSA) IR form based analysis can be applied in PSA form. The gamma function in PSA form keeps all essential control flow information and eliminates unnecessary predicates at the same time.

Abstract: A method for statement shifting to increase the parallelism of loops includes constructing a data dependence graph (DDG) to represent dependences between statements in a loop, constructing a basic equations group from the DDG, constructing a dependence equations group derived in part from the basic equations group, and determining a shifting vector for the loop from the dependence equations group, wherein the shifting vector to represent an offset to apply to each statement in the loop for statement shifting. Other embodiments are also disclosed.

Abstract: Methods for optimizing stream operator processing by creating a system of inequalities to describe a multi-dimensional polyhedron, solving the system by projecting the polyhedron into a space of one fewer dimensions, and mapping the solution into the stream program. Other program optimization methods based on affine partitioning are also described and claimed.

Abstract: A method including providing a stream of content to a processor, transforming kernels within the stream of content through affine modeling, transforming the affine modeled kernels, stream contracting kernel processes, and stream blocking the kernel processes.

Abstract: A method is provided of operating a mass spectrometer apparatus comprising a pair of quadrupole rod sets. Each quadrupole rod set is operated in a mass resolving mode. They may be operated in the same or different stability regions. The rod sets are operated to select essentially ions of the same mass to charge ratio, and are operated such that the combined resolution of the two rod sets is greater than the resolution of either rod set. The rod sets can be operated at relatively low resolution, with the combined peak shape from the two rod sets showing high resolution. This can make up for mechanical imperfections in the rod sets, losses due to high gas pressures, etc. A mass shift can be provided to give the desired resolution. The rod sets can be close coupled, and for this purpose neutralizing capacitors can be provided to prevent electrical interference between adjacent rod sets.