Abstract: A method for diagnosing a faulty board includes generating a table of debug knowledge in accordance with predefined debug rules, and configuring a diagnostic engine in accordance with the table of debug knowledge. The method also includes subjecting the faulty board to the diagnostic engine to generate a suggested repair, receiving feedback regarding an effectiveness of the suggested repair, and reconfiguring the diagnostic engine in accordance with the feedback regarding the effectiveness of the suggested repair.

Abstract: A method for diagnosing a faulty board includes generating a table of debug knowledge in accordance with predefined debug rules, and configuring a diagnostic engine in accordance with the table of debug knowledge. The method also includes subjecting the faulty board to the diagnostic engine to generate a suggested repair, receiving feedback regarding an effectiveness of the suggested repair, and reconfiguring the diagnostic engine in accordance with the feedback regarding the effectiveness of the suggested repair.

Abstract: An example method is provided and includes collecting inputs for a circuit board under test; evaluating historical repair records using a neuron network; providing repair actions for the circuit board based on the historical repair records; and providing an output reflecting a particular component of the circuit board to be replaced or to be repaired, where the output is associated with a developed probability of successfully fixing an issue that was identified by the test. In more specific implementations, the inputs include fault syndromes and log files associated with the circuit board under test. Additionally, at least one of the inputs of the neuron network is a syndrome vector extracted from a failure log. In yet other instances, particular outputs having higher probabilities are selected as the repair actions. The neuron network can be weighted using diagnosis knowledge weights.

Abstract: Power switching circuits and power management techniques are provided that can reduce static power of ICs, including digital core processors. In one embodiment, the power switching circuit includes a footer (power-gating transistor) between the core and a ground rail and at least two additional power-gating transistors parallel to the footer. The power-gating transistors are controlled by respective control signals to enable selective switching. In a specific embodiment, for each sleep mode, at most, a single one of the transistors is turned on. Multiple sleep modes are accomplished according to the relative sizing of the additional power-gating transistors. A larger of the additional transistors is used to provide a standby mode during short idling times by providing a fast wake-up time and some reduction in static power. For standby modes during longer idling periods, smaller sized transistors are turned on. For longest idling periods, all transistors are turned off.

Abstract: An example method is provided and includes collecting inputs for a circuit board under test; evaluating historical repair records using a neuron network; providing repair actions for the circuit board based on the historical repair records; and providing an output reflecting a particular component of the circuit board to be replaced or to be repaired, where the output is associated with a developed probability of successfully fixing an issue that was identified by the test. In more specific implementations, the inputs include fault syndromes and log files associated with the circuit board under test. Additionally, at least one of the inputs of the neuron network is a syndrome vector extracted from a failure log. In yet other instances, particular outputs having higher probabilities are selected as the repair actions. The neuron network can be weighted using diagnosis knowledge weights.

Abstract: Power switching circuits and power management techniques are provided that can reduce static power of ICs, including digital core processors. In one embodiment, the power switching circuit includes a footer (power-gating transistor) between the core and a ground rail and at least two additional power-gating transistors parallel to the footer. The power-gating transistors are controlled by respective control signals to enable selective switching. In a specific embodiment, for each sleep mode, at most, a single one of the transistors is turned on. Multiple sleep modes are accomplished according to the relative sizing of the additional power-gating transistors. A larger of the additional transistors is used to provide a standby mode during short idling times by providing a fast wake-up time and some reduction in static power. For standby modes during longer idling periods, smaller sized transistors are turned on. For longest idling periods, all transistors are turned off.