Abstract: Disclosed are a hardware acceleration apparatus and an acceleration method for neural network computing. The hardware acceleration apparatus comprises a memory module, a parsing module and a plurality of functional modules, wherein the memory module is used for caching data required by neural network computing; the parsing module is used for receiving an instruction sequence that is predetermined according to the size of the memory module and the data required by neural network computing, for parsing the instruction sequence so as to obtain a plurality of types of operation instructions, and for issuing a corresponding type of operation instruction to each functional module; and each functional module is used for executing a corresponding operation of neural network computing in response to the reception of the corresponding type of operation instruction. By using the hardware acceleration apparatus for neural network computing, the universality of the hardware acceleration apparatus can be improved.

Abstract: In one aspect, an operation method based on a neural network: calculating, according to the sizes of a convolution kernel and an original image, a total number of operation cycles and an image matrix corresponding to each operation cycle; for the image matrix, a plurality of operation units concurrently acquiring the image data and performing a product operation on the image data and pre-stored weight data, to obtain intermediate data; summing the intermediate data to obtain an operation result; and compiling statistics on all the operation results to obtain a target operation result. The overall operation speed is increased in a unit time; the data read logic is simplified; and the bandwidth requirement of a single operation unit for data is reduced. A convolution operation of any size can be performed, and the convolution operation efficiency is improved, thereby increasing the image processing speed.