Abstract: An array substrate is disclosed herein, which includes a substrate, a plurality of signal lines, and conductive layer. The plurality of signal lines are disposed over the substrate, and have at least two signal lines insulated and staggered from one another to thereby form at least one signal line-staggered region at each site of staggering. It is configured such that a first zone formed by an orthographic projection of the at least one signal line-staggered region on the substrate is configured to have a gap with a second zone formed by an orthographic projection of the conductive layer on the substrate excluding the first zone. The array substrate can be a thin-film transistor array substrate, where the plurality of signal lines can include a common signal line and a plurality of gate lines, and the common signal line can be staggered with each gate line at a signal line-staggered region.

Abstract: An array substrate is disclosed herein, which includes a substrate, a plurality of signal lines, and conductive layer. The plurality of signal lines are disposed over the substrate, and have at least two signal lines insulated and staggered from one another to thereby form at least one signal line-staggered region at each site of staggering. It is configured such that a first zone formed by an orthographic projection of the at least one signal line-staggered region on the substrate is configured to have a gap with a second zone formed by an orthographic projection of the conductive layer on the substrate excluding the first zone. The array substrate can be a thin-film transistor array substrate, where the plurality of signal lines can include a common signal line and a plurality of gate lines, and the common signal line can be staggered with each gate line at a signal line-staggered region.