Patents by Inventor Zhaohui Ma
Zhaohui Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240008521Abstract: Disclosed is a device and method for reducing combustion cone fallout propensity and stabilizing loss of tobacco from ends. Firstly, the right installation positioning hole is moved rightwards to extend the distance of the separation zone. Meanwhile, the vibration mechanism is redesigned so that it is enabled to move toward the lower right of the material groove body. Therefore, there is enough space to install the separation screen in the separation zone. Finally, the separation screen is installed. The tobacco scraps are separated out when they pass through the separation screen, thus reducing cone dropping when the cigarette burns, stabilizing the amount of dropping tobacco at the end, and improving the smoking experience and recognition of customers with regard to cigarette products.Type: ApplicationFiled: July 5, 2023Publication date: January 11, 2024Inventors: Zhen Wang, Peng Ji, Jianlong Zhang, Duanduan Li, Laihong Zhou, Zhaohui Ma, Jiansheng Yang, Xin Zhao, Huge Liu, Xiaojun Zhang, Yan Li, Xuena Song
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Publication number: 20230380159Abstract: A memory array comprises strings of memory cells. The memory array comprises laterally-spaced memory blocks that individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The channel material of the channel-material strings directly electrically couples to conductor material of the conductor tier. Individual ones of the channel-material strings in a vertical cross-section comprise an external jog surface that is above the conductor tier and an internal jog surface that is in the conductor tier. Other aspects, including methods, are disclosed.Type: ApplicationFiled: May 18, 2022Publication date: November 23, 2023Applicant: Micron Technology, Inc.Inventors: Damir Fazil, John D. Hopkins, Indra V. Chary, Tom John, Joel D. Peterson, Kar Wui Thong, Zhaohui Ma
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Patent number: 11705425Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.Type: GrantFiled: April 15, 2021Date of Patent: July 18, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Benjamin L. McClain, Brandon P. Wirz, Zhaohui Ma
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Patent number: 11670612Abstract: A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.Type: GrantFiled: February 15, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Brandon P. Wirz, Benjamin L. McClain, Jeremy E. Minnich, Zhaohui Ma
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Publication number: 20230148655Abstract: The present invention relates to a cut-stem separating and baffling apparatus and a primary air separation apparatus. The cut-stem separating and baffling apparatus includes a cut-stem separating baffle and struts; and the strut includes a base, a hanging panel, and an inner hexagon adjustment bolt, where the base includes a connecting segment and a support segment that are connected to each other, where the connecting segment is located above the cut-stem separating baffle, and the support segment is located behind the cut-stem separating baffle; the hanging panel includes a transverse hanging panel, and a longitudinal hanging panel, and a connecting hanging panel is disposed in a direction of the longitudinal hanging panel toward the cut-stem separating baffle, where the connecting hanging panel is connected to the cut-stem separating baffle; and the connecting segment of the base is connected to the transverse hanging panel using the inner hexagon adjustment bolt.Type: ApplicationFiled: January 19, 2023Publication date: May 18, 2023Inventors: Zhen Wang, Shubin Jin, Peng Ji, Jianlong Zhang, Duanduan Li, Laihong Zhou, Huge Liu, Xiaohua Yang, Zhaohui Ma
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Publication number: 20210233887Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.Type: ApplicationFiled: April 15, 2021Publication date: July 29, 2021Inventors: Benjamin L. McClain, Brandon P. Wirz, Zhaohui Ma
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Publication number: 20210183802Abstract: A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.Type: ApplicationFiled: February 15, 2021Publication date: June 17, 2021Inventors: BRANDON P. WIRZ, BENJAMIN L. MCCLAIN, JEREMY E. MINNICH, ZHAOHUI MA
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Publication number: 20210175194Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.Type: ApplicationFiled: February 12, 2021Publication date: June 10, 2021Inventors: Aibin Yu, Wei Zhou, Zhaohui Ma
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Patent number: 11024595Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.Type: GrantFiled: June 16, 2017Date of Patent: June 1, 2021Assignee: Micron Technology, Inc.Inventors: Benjamin L. McClain, Brandon P. Wirz, Zhaohui Ma
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Patent number: 10923448Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.Type: GrantFiled: June 19, 2017Date of Patent: February 16, 2021Assignee: Micron Technology, Inc.Inventors: Aibin Yu, Wei Zhou, Zhaohui Ma
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Patent number: 10734370Abstract: Methods of making semiconductor device packages may involve cutting kerfs in streets between regions of a semiconductor wafer and positioning stacks of semiconductor dice on portions of surfaces of at least some adjacent regions. A protective material may be dispensed only between the stacks of the semiconductor dice, over the exposed remainders of the regions, and in the kerfs. A back side of the semiconductor wafer may be ground to a final thickness, revealing the protective material in the kerfs at a side of the semiconductor wafer opposite the stacks of the semiconductor dice. The protective material between the stacks of the semiconductor dice and within the kerfs may be cut through, leaving the protective material on sides of the semiconductor dice of the stacks and on side surfaces of the regions within the kerfs.Type: GrantFiled: April 26, 2019Date of Patent: August 4, 2020Assignee: Micron Technology, Inc.Inventors: Zhaohui Ma, Wei Zhou, Chee Chung So, Soo Loo Ang, Aibin Yu
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Patent number: 10636678Abstract: Methods for forming semiconductor die assemblies with heat transfer features are disclosed herein. In some embodiments, the methods comprise providing a wafer having a first side and a second side opposite the first side, attaching a semiconductor die stack to the first side of the wafer, and forming a plurality of heat transfer features at the second side of the wafer. The heat transfer features can be defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer.Type: GrantFiled: November 28, 2018Date of Patent: April 28, 2020Assignee: Micron Technology, Inc.Inventors: Wei Zhou, Zhaohui Ma, Aibin Yu
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Publication number: 20190252362Abstract: Methods of making semiconductor device packages may involve cutting kerfs in streets between regions of a semiconductor wafer and positioning stacks of semiconductor dice on portions of surfaces of at least some adjacent regions. A protective material may be dispensed only between the stacks of the semiconductor dice, over the exposed remainders of the regions, and in the kerfs. A back side of the semiconductor wafer may be ground to a final thickness, revealing the protective material in the kerfs at a side of the semiconductor wafer opposite the stacks of the semiconductor dice. The protective material between the stacks of the semiconductor dice and within the kerfs may be cut through, leaving the protective material on sides of the semiconductor dice of the stacks and on side surfaces of the regions within the kerfs.Type: ApplicationFiled: April 26, 2019Publication date: August 15, 2019Inventors: Zhaohui Ma, Wei Zhou, Chee Chung So, Soo Loo Ang, Aibin Yu
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Patent number: 10312226Abstract: Methods of protecting semiconductor devices may involve cutting partially through a thickness of a semiconductor wafer to form trenches between stacks of semiconductor dice on regions of integrated circuitry of the semiconductor wafer. A protective material may be dispensed into the trenches and to a level at least substantially the same as a height of the stacks of semiconductor dice. Material of the semiconductor wafer may be removed from a back side thereof at least to a depth sufficient to expose the protective material in the trenches. A remaining thickness of the protective material between the stacks of semiconductor dice may be cut through.Type: GrantFiled: October 9, 2017Date of Patent: June 4, 2019Assignee: Micron Technology, Inc.Inventors: Zhaohui Ma, Wei Zhou, Chee Chung So, Soo Loo Ang, Aibin Yu
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Publication number: 20190109019Abstract: Methods for forming semiconductor die assemblies with heat transfer features are disclosed herein. In some embodiments, the methods comprise providing a wafer having a first side and a second side opposite the first side, attaching a semiconductor die stack to the first side of the wafer, and forming a plurality of heat transfer features at the second side of the wafer. The heat transfer features can be defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer.Type: ApplicationFiled: November 28, 2018Publication date: April 11, 2019Inventors: Wei Zhou, Zhaohui Ma, Aibin Yu
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Publication number: 20190067232Abstract: A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Inventors: BRANDON P. WIRZ, BENJAMIN L. MCCLAIN, JEREMY E. MINNICH, ZHAOHUI MA
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Publication number: 20180366434Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.Type: ApplicationFiled: June 16, 2017Publication date: December 20, 2018Inventors: Benjamin L. McClain, Brandon P. Wirz, Zhaohui Ma
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Patent number: 10153178Abstract: Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.Type: GrantFiled: July 20, 2017Date of Patent: December 11, 2018Assignee: Micron Technology, Inc.Inventors: Wei Zhou, Zhaohui Ma, Aibin Yu
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Patent number: 10103134Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.Type: GrantFiled: October 9, 2017Date of Patent: October 16, 2018Inventors: Wei Zhou, Aibin Yu, Zhaohui Ma, Sony Varghese, Jonathan S. Hacker, Bret K. Street, Shijian Luo
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Publication number: 20180033781Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.Type: ApplicationFiled: October 9, 2017Publication date: February 1, 2018Inventors: Wei Zhou, Aibin Yu, Zhaohui Ma, Sony Varghese, Jonathan S. Hacker, Bret K. Street, Shijian Luo