Patents by Inventor Zhaohui Shan

Zhaohui Shan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9988850
    Abstract: A downhole seal system for roller cone drill bits includes a seal gland having a width larger than it depth. In one implementation, the seal gland includes a protrusion along its base on which a seal element seats. The seal element is a single, annular seal element with a recess formed therein so as to define two lobes. The seal element seats in the gland so that the recess engages the protrusion. The lobes function as separate seal elements, although they are a single unitary seal element disposed in a single gland.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: June 5, 2018
    Assignee: HALLIBURTON ENERGY SERVICES, INC.
    Inventors: Micheal B. Crawford, Mark E. Williams, Young H. Lee, David P. Duckworth, Zhaohui Shan
  • Publication number: 20150345226
    Abstract: A downhole seal system for roller cone drill bits includes a seal gland having a width larger than it depth. In one implementation, the seal gland includes a protrusion along its base on which a seal element seats. The seal element is a single, annular seal element with a recess formed therein so as to define two lobes. The seal element seats in the gland so that the recess engages the protrusion. The lobes function as separate seal elements, although they are a single unitary seal element disposed in a single gland.
    Type: Application
    Filed: December 31, 2012
    Publication date: December 3, 2015
    Inventors: Michael B. Crawford, Mark E. Williams, Young H. Lee, David P. Duckworth, Zhaohui Shan
  • Patent number: 7884634
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: February 8, 2011
    Assignee: Verigy (Singapore) Pte, Ltd
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Patent number: 7872482
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: January 18, 2011
    Assignee: Verigy (Singapore) Pte. Ltd
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Publication number: 20090153165
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Application
    Filed: January 15, 2009
    Publication date: June 18, 2009
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Publication number: 20080246500
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Application
    Filed: September 19, 2007
    Publication date: October 9, 2008
    Inventors: Fu Chiung CHONG, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Patent number: 7382142
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: June 3, 2008
    Assignee: NanoNexus, Inc.
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Publication number: 20050275418
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Application
    Filed: May 18, 2005
    Publication date: December 15, 2005
    Inventors: Fu Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank Swiatowiec, Zhaohui Shan