Patents by Inventor Zhaohui Shan
Zhaohui Shan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9988850Abstract: A downhole seal system for roller cone drill bits includes a seal gland having a width larger than it depth. In one implementation, the seal gland includes a protrusion along its base on which a seal element seats. The seal element is a single, annular seal element with a recess formed therein so as to define two lobes. The seal element seats in the gland so that the recess engages the protrusion. The lobes function as separate seal elements, although they are a single unitary seal element disposed in a single gland.Type: GrantFiled: December 31, 2012Date of Patent: June 5, 2018Assignee: HALLIBURTON ENERGY SERVICES, INC.Inventors: Micheal B. Crawford, Mark E. Williams, Young H. Lee, David P. Duckworth, Zhaohui Shan
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Publication number: 20150345226Abstract: A downhole seal system for roller cone drill bits includes a seal gland having a width larger than it depth. In one implementation, the seal gland includes a protrusion along its base on which a seal element seats. The seal element is a single, annular seal element with a recess formed therein so as to define two lobes. The seal element seats in the gland so that the recess engages the protrusion. The lobes function as separate seal elements, although they are a single unitary seal element disposed in a single gland.Type: ApplicationFiled: December 31, 2012Publication date: December 3, 2015Inventors: Michael B. Crawford, Mark E. Williams, Young H. Lee, David P. Duckworth, Zhaohui Shan
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Patent number: 7884634Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.Type: GrantFiled: January 15, 2009Date of Patent: February 8, 2011Assignee: Verigy (Singapore) Pte, LtdInventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
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Patent number: 7872482Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.Type: GrantFiled: September 19, 2007Date of Patent: January 18, 2011Assignee: Verigy (Singapore) Pte. LtdInventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
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Publication number: 20090153165Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.Type: ApplicationFiled: January 15, 2009Publication date: June 18, 2009Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
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Publication number: 20080246500Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.Type: ApplicationFiled: September 19, 2007Publication date: October 9, 2008Inventors: Fu Chiung CHONG, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
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Patent number: 7382142Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.Type: GrantFiled: May 18, 2005Date of Patent: June 3, 2008Assignee: NanoNexus, Inc.Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
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Publication number: 20050275418Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.Type: ApplicationFiled: May 18, 2005Publication date: December 15, 2005Inventors: Fu Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank Swiatowiec, Zhaohui Shan