Patents by Inventor Zhaojun Tian

Zhaojun Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120112333
    Abstract: A molded surface mount semiconductor device has electrical contact elements disposed in a set of pairs of zigzag rows extending adjacent and generally parallel to opposite edges of an active face of a semiconductor die. Each of the pairs of rows includes an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements. The electrical contact elements of the inner and outer zigzag rows are partially inter-digitated. A lead frame used in making the device also has a die pad located inside the set of pairs of zigzag rows, and an outer frame element located outside the set of pairs of zigzag rows, and which support the electrical contact elements of the inner and outer zigzag rows respectively.
    Type: Application
    Filed: August 16, 2011
    Publication date: May 10, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Qiang Liu, Qingchun He, Zhaojun Tian
  • Publication number: 20110241187
    Abstract: A lead frame having a recessed die bond area. The lead frame has top and bottom surfaces and a first lead frame thickness defined as the distance between the top and bottom surfaces. The lead frame has a die bond area surface located within a reduced die bond area. A second thickness is defined as the distance between the die bond area surface and the bottom surface. The second lead frame thickness is less than the first lead frame thickness such that a semiconductor die disposed and attached to the die bond area surface has a reduced overall package thickness. A side wall formed between the die bond area surface and the top surface contains the adhesive material used to attach the die, which reduces adhesive bleeding and prevents wire bonding contamination.
    Type: Application
    Filed: February 1, 2011
    Publication date: October 6, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Liping Guo, Qingchun He, Zhaojun Tian, Jie Yang
  • Publication number: 20110193207
    Abstract: A lead frame for providing electrical interconnection to a semiconductor die has a generally rectangular flag area having first and second major surfaces and four sides. The flag area is sized and shaped to receive a semiconductor die on one of the first and second major surfaces. A first row of leads is located adjacent to a first one of the four sides of the flag area and a second row of leads is located adjacent to a second one of the four sides of the flag area, where the second one of the four sides is adjacent to the first one of the four sides. The remaining two sides do not have any adjacent leads.
    Type: Application
    Filed: January 11, 2011
    Publication date: August 11, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Zhaojun Tian, Qingchun He, Qiang Liu, Jie Yang, Shufeng Zhao