Abstract: A serial data transmission system includes a sending terminal for sending data, a receiving terminal for receiving the data sent by the sending terminal, a first connecting capacitor connected between the sending terminal and the receiving terminal, and a second connected capacitor connected between the sending terminal and the receiving terminal. The sending terminal includes a sending terminal driving unit, and an amplitude detecting unit connected to the sending terminal driving unit. The sending terminal driving unit outputs a pair of differential signals according to signals of the received data. The amplitude detecting unit detects changes in amplitudes of the differential signals outputted by the sending terminal driving unit, and outputs an indicating signal for indicating whether the sending terminal is properly connected to the receiving terminal. A serial data transmission method is further provided.

Abstract: An LC oscillator process compensation circuit includes an LC oscillator, a reference voltage terminal, a follower and a current auxiliary circuit, the LC oscillator includes a gain stage, an inductor and two voltage-controlled capacitors, the gain stage includes a first Field Effect Transistor, a second Field Effect Transistor, a third Field Effect Transistor and a fourth Field Effect Transistor, the current auxiliary circuit is connected with an external power source and the follower that connected with the reference voltage terminal to provide a working voltage for the LC oscillator, the follower includes a detection circuit to detecting current changes of the gain stage. The LC oscillator process compensation circuit has simple circuit structure and eliminates frequency changes of the LC oscillator caused by the process variations of the gain stage, thereby ensuring stability of the frequency of the LC oscillator, improving work precision and reducing design difficult.

Abstract: An equalization circuit, includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first regulating circuit, a second regulating circuit, and a bias voltage generating circuit. The bias voltage generating circuit is connected with both the first regulating circuit and the second regulating circuit. The first regulating circuit includes a first field effect transistor (FET), a second FET, a third FET, a fourth FET, a first resistor connected with the first FET, a second resistor connected with the second FET, a third resistor connected with the third FET, a fourth resistor connected with the fourth FET, a fifth resistor connected with the third FET, a sixth resistor connected with the fourth FET, a first capacitor connected with the third FET, and a second capacitor connected with the fourth FET. An equalization system is further provided.

Abstract: An LC oscillator process compensation circuit includes an LC oscillator, a reference voltage terminal, a follower and a current auxiliary circuit, the LC oscillator includes a gain stage, an inductor and two voltage-controlled capacitors, the gain stage includes a first Field Effect Transistor, a second Field Effect Transistor, a third Field Effect Transistor and a fourth Field Effect Transistor, the current auxiliary circuit is connected with an external power source and the follower that connected with the reference voltage terminal to provide a working voltage for the LC oscillator, the follower includes a detection circuit to detecting current changes of the gain stage. The LC oscillator process compensation circuit has simple circuit structure and eliminates frequency changes of the LC oscillator caused by the process variations of the gain stage, thereby ensuring stability of the frequency of the LC oscillator, improving work precision and reducing design difficult.

Abstract: An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.

Abstract: A serial data transmission system includes a sending terminal for sending data, a receiving terminal for receiving the data sent by the sending terminal, a first connecting capacitor connected between the sending terminal and the receiving terminal, and a second connected capacitor connected between the sending terminal and the receiving terminal. The sending terminal includes a sending terminal driving unit, and an amplitude detecting unit connected to the sending terminal driving unit. The sending terminal driving unit outputs a pair of differential signals according to signals of the received data. The amplitude detecting unit detects changes in amplitudes of the differential signals outputted by the sending terminal driving unit, and outputs an indicating signal for indicating whether the sending terminal is properly connected to the receiving terminal. A serial data transmission method is further provided.

Abstract: A serial data transmission system, includes a transmitting terminal for transmitting a data, a receiving terminal for receiving the data transmitted by the transmitting terminal, a first connecting capacitor connected between the transmitting terminal and the receiving terminal, and a second connecting capacitor connected between the transmitting terminal and the receiving terminal, wherein the transmitting terminal comprises a transmitting terminal driver unit and an amplitude detection unit connected with the transmitting terminal driver unit, the transmitting terminal driver unit outputs a pair of differential signals, the amplitude detection unit detects an amplitude variation of the differential signals output by the transmitting terminal driver unit, and outputs an indication signal indicating whether the transmitting terminal and the receiving terminal are properly connected with each other. A serial data transmission method is further provided.

Abstract: A clock generation circuit, includes a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator. The present invention has simple structure, small process variation, and lower cost, and is able to improve the accuracy of the clock with maximum possibility.

Abstract: An equalization circuit, includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first regulating circuit, a second regulating circuit, and a bias voltage generating circuit. The bias voltage generating circuit is connected with both the first regulating circuit and the second regulating circuit. The first regulating circuit includes a first field effect transistor (FET), a second FET, a third FET, a fourth FET, a first resistor connected with the first FET, a second resistor connected with the second FET, a third resistor connected with the third FET, a fourth resistor connected with the fourth FET, a fifth resistor connected with the third FET, a sixth resistor connected with the fourth FET, a first capacitor connected with the third FET, and a second capacitor connected with the fourth FET. An equalization system is further provided.

Abstract: A serial data transmission system, includes a transmitting terminal for transmitting a data, a receiving terminal for receiving the data transmitted by the transmitting terminal, a first connecting capacitor connected between the transmitting terminal and the receiving terminal, and a second connecting capacitor connected between the transmitting terminal and the receiving terminal, wherein the transmitting terminal comprises a transmitting terminal driver unit and an amplitude detection unit connected with the transmitting terminal driver unit, the transmitting terminal driver unit outputs a pair of differential signals, the amplitude detection unit detects an amplitude variation of the differential signals output by the transmitting terminal driver unit, and outputs an indication signal indicating whether the transmitting terminal and the receiving terminal are properly connected with each other. A serial data transmission method is further provided.

Abstract: A duty cycle adjusting system includes a detection circuit, a first clock signal adjusting circuit connected with the detection circuit, and a second clock signal adjusting circuit connected with the detection circuit, wherein the detection circuit detects a duty cycle of a first output signal outputted by the first clock signal adjusting circuit and a duty cycle of a second output signal outputted by the second clock signal adjusting circuit, and outputs a first detection signal and a second detection signal, the first and second output signals are a pair of differential clock signals, the first and second detection signals are adapted for respectively adjusting rising edges of the pair of differential clock signals. No peripheral circuit is needed to provide the bias in the duty cycle adjusting system. The duty cycle adjusting system has the simple structure and can be independently applied to the clock path.

Abstract: An equalization system includes an adjustable equalization unit, a common-mode feedback unit connected with the equalization unit, a current balance driving unit connected with the feedback and equalization units, a first high-pass filter unit connected with the equalization unit, a second high-pass filter unit connected with the driving unit, a first low-pass filter unit connected with the equalization unit, a second low-pass filter unit connected with the driving unit, a first energy detection unit connected with two high-pass filter units, a second energy detection unit connected with two low-pass filter units, a first analog-to-digital converter unit connected with the first energy detection unit, a second analog-to-digital converter unit connected with the second energy detection unit and a state decision unit connected with two analog-to-digital converter units outputs a control signal for adjusting the equalization unit.

Abstract: A duty cycle adjusting system includes a detection circuit, a first clock signal adjusting circuit connected with the detection circuit, and a second clock signal adjusting circuit connected with the detection circuit, wherein the detection circuit detects a duty cycle of a first output signal outputted by the first clock signal adjusting circuit and a duty cycle of a second output signal outputted by the second clock signal adjusting circuit, and outputs a first detection signal and a second detection signal, the first and second output signals are a pair of differential clock signals, the first and second detection signals are adapted for respectively adjusting rising edges of the pair of differential clock signals. No peripheral circuit is needed to provide the bias in the duty cycle adjusting system. The duty cycle adjusting system has the simple structure and can be independently applied to the clock path.

Abstract: A clock generation circuit, includes a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator. The present invention has simple structure, small process variation, and lower cost, and is able to improve the accuracy of the clock with maximum possibility.

Abstract: A timing error correction method used at the transmitting end in high-speed serial data transmission system comprises inputting a predefined parallel data training sequence and a clock signal, converting the training sequence into serial data, counting the number of the rising or falling edges of the serial data within a certain period, sending an adjustment signal for adjusting the time delay of the clock signal, obtaining a reasonable serialization timing, so that the number of the rising edges or falling edges of the serial data being equal to a predefined correct number. The corresponding timing error correction system comprises a data path, an adjustable delay clock path, a serialization unit for converting the parallel data into serial data, a driver unit, and a counting judging unit for counting the number of the rising or falling edges of the serial data and sending an adjustment signal to the adjustable delay clock path so as to control the timing of the serialization unit.

Abstract: An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.

Abstract: An equalization system includes an adjustable equalization unit, a common-mode feedback unit connected with the equalization unit, a current balance driving unit connected with the feedback and equalization units, a first high-pass filter unit connected with the equalization unit, a second high-pass filter unit connected with the driving unit, a first low-pass filter unit connected with the equalization unit, a second low-pass filter unit connected with the driving unit, a first energy detection unit connected with two high-pass filter units, a second energy detection unit connected with two low-pass filter units, a first analog-to-digital converter unit connected with the first energy detection unit, a second analog-to-digital converter unit connected with the second energy detection unit and a state decision unit connected with two analog-to-digital converter units outputs a control signal for adjusting the equalization unit.