Abstract: The present application discloses a method for manufacturing a metal gate of a PMOS, comprising: step 1, forming a P-type work function metal layer; step 2, depositing an N-type work function metal layer by means of a PVD process, wherein over a bottom surface of a gate trench, the N-type work function metal layer has a hill profile; step 3, forming a first top barrier metal sublayer by means of a conformal growth process, wherein the first top barrier metal sublayer completely fills a sharp corner area of the N-type work function metal layer at a corner of the gate trench; step 4, growing a second top barrier metal sublayer by means of a PVD bombardment process; step 5, forming a third top barrier metal sublayer and a fourth top barrier metal sublayer; and step 6, forming a metal conductive material layer.

Abstract: The present disclosure provides a method for reducing a resistance of a contact, including: preparing a via in a device structure, and fabricating an adhesive layer that is in the via and attached to an inner wall of the via; fabricating a metal film that is in the via and attached to the adhesive layer; and filling the via with metal tungsten. In the present application, from the point of view of reducing high-resistance metals Ti and TiN and increasing low-resistance metal tungsten, a fluorine-free chemical is used to replace WF6 to participate in a reaction of a W film, forming a tungsten film which replaces a TiN film, increasing the volume of tungsten, and reducing a via resistance.

Abstract: The present application discloses a method for manufacturing a metal gate of a PMOS, comprising: step 1, forming a P-type work function metal layer; step 2, depositing an N-type work function metal layer by means of a PVD process, wherein over a bottom surface of a gate trench, the N-type work function metal layer has a hill profile; step 3, forming a first top barrier metal sublayer by means of a conformal growth process, wherein the first top barrier metal sublayer completely fills a sharp corner area of the N-type work function metal layer at a corner of the gate trench; step 4, growing a second top barrier metal sublayer by means of a PVD bombardment process; step 5, forming a third top barrier metal sublayer and a fourth top barrier metal sublayer; and step 6, forming a metal conductive material layer.

Abstract: The present application discloses a contact, which comprises a contact opening, and a Ti layer, a glue layer and a tungsten layer which completely fill the contact opening; the Ti layer is subjected to annealing treatment; the tungsten layer comprises a tungsten seed layer and a tungsten body layer; the glue layer consists of a TiN layer which is divided into a plurality of TiN sub-layers, all or part of the TiN sub-layers are subjected to the annealing treatment, and the size of grains of the TiN sub-layer subjected to the annealing treatment is limited by the thickness of the corresponding TiN sub-layer. The present application further discloses a method for making a contact. The present application can prevent the annealing treatment of the TiSi layer from producing large lattice grains in the glue layer, thus can make the tungsten seed layer be a continuous structure.

Abstract: The present application discloses a copper filled recess structure, which comprises a recess formed in a first dielectric layer; a block layer is formed on the bottom surface and side surfaces of the recess; a cobalt layer and a ruthenium layer are formed on the surface of the block layer; a copper layer completely fills the recess; a supportive nucleation film layer of the copper layer is formed by superposing the cobalt layer and the ruthenium layer. The present application further discloses a method for making a copper filled recess structure. Since the copper layer in the present application does not contain a copper seed layer and completely consists of the electrochemically-plated copper film, the ability of filling copper in the recess can be improved, and it is especially suitable for use as a copper connection and a via at a process node of less than 14 nm.