Abstract: This application discloses a MEMS chip structure, including a substrate, a side wall, a dielectric plate, a MEMS micromirror array, and a grid array, where the MEMS micromirror array includes a plurality of grooves and a plurality of MEMS micromirrors. The plurality of MEMS micromirrors are in a one-to-one correspondence with the plurality of grooves. The grid array is located above the MEMS micromirror array, and a lower surface of the grid array is connected to upper surfaces of side walls of at least some of the plurality of grooves.

Abstract: This application discloses a MEMS chip structure, including a substrate, a side wall, a dielectric plate, a MEMS micromirror array, and a grid array, where the MEMS micromirror array includes a plurality of grooves and a plurality of MEMS micromirrors. The plurality of MEMS micromirrors are in a one-to-one correspondence with the plurality of grooves. The grid array is located above the MEMS micromirror array, and a lower surface of the grid array is connected to upper surfaces of side walls of at least some of the plurality of grooves.

Abstract: There is provided a method for determining a noise exposure level associated as the cause of an observed evolution of hearing acuity of an individual of known gender.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a PIP capacitor located. The PIP capacitor includes a first polysilicon layer, a metallic silicide layer, a protective layer, a dielectric layer, and a second polysilicon layer, which have a lower conductive plate pattern and are successively arranged. The method includes: providing a substrate; successively forming a first polysilicon layer, a metallic silicide, and a protective layer on the substrate; transferring a lower conductive plate pattern into the first polysilicon layer, the metallic silicide layer, and the protective layer, thus forming the first polysilicon layer, the metallic silicide layer, and the protective layer having the lower conductive plate pattern; successively forming a dielectric layer and a second polysilicon layer having a lower conductive plate pattern on the protective layer. The capacitance and reliability of the PIP capacitor are improved.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a PIP capacitor located. The PIP capacitor includes a first polysilicon layer, a metallic silicide layer, a protective layer, a dielectric layer, and a second polysilicon layer, which have a lower conductive plate pattern and are successively arranged. The method includes: providing a substrate; successively forming a first polysilicon layer, a metallic silicide, and a protective layer on the substrate; transferring a lower conductive plate pattern into the first polysilicon layer, the metallic silicide layer, and the protective layer, thus forming the first polysilicon layer, the metallic silicide layer, and the protective layer having the lower conductive plate pattern; successively forming a dielectric layer and a second polysilicon layer having a lower conductive plate pattern on the protective layer. The capacitance and reliability of the PIP capacitor are improved.