Abstract: A semiconductor structure includes a substrate; a first electrode layer over the substrate; a dielectric layer on a sidewall surface of the first electrode layer; and a second electrode layer over the substrate. The first electrode layer, the dielectric layer, and the second electrode layer are arranged in a direction parallel to a surface of the substrate.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate, sequentially forming a first protective layer and a second protective layer on the substrate, etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column, removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column, removing a remaining portion of the second protective layer, and forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column. The first contact material layer in contact with the lower portion of the semiconductor column does not increase the source series resistance.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate, sequentially forming a first protective layer and a second protective layer on the substrate, etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column, removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column, removing a remaining portion of the second protective layer, and forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column. The first contact material layer in contact with the lower portion of the semiconductor column does not increase the source series resistance.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate, sequentially forming a first protective layer and a second protective layer on the substrate, etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column, removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column, removing a remaining portion of the second protective layer, and forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column. The first contact material layer in contact with the lower portion of the semiconductor column does not increase the source series resistance.

Abstract: A semiconductor device includes a substrate, a semiconductor column vertically disposed on the substrate, a first contact material layer on the substrate and in contact with a lower portion of the semiconductor column, a first insulating material layer on the first contact material layer and having an upper surface lower than an upper surface of the semiconductor column, a gate dielectric material layer on the first insulating material layer and on a portion of sidewalls of the semiconductor column while exposing an upper portion of the semiconductor column, and a gate stack structure on the gate dielectric material layer and surrounding a portion of the gate dielectric material layer on the sidewalls of the semiconductor column. The gate stack structure includes from inside to outside a P-type work function layer, an N-type work function layer, and a gate.

Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. This inventive concept reduces the loss of the interlayer dielectric layer, thus reduces the height loss of the gate electrode.

Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. This inventive concept reduces the loss of the interlayer dielectric layer, thus reduces the height loss of the gate electrode.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a semiconductor fin on a substrate, and a trench isolation structure surrounding the fin and having an upper surface flush with an upper surface of the fin and including first and second trench isolation portions on opposite sides of the fin along the fin longitudinal direction, and third and fourth trench isolation portions on distal ends of the fin along a second direction intersecting the longitudinal direction; forming a patterned first hardmask layer having an opening exposing an upper surface of the third and fourth trench isolation portions; and forming a first insulator layer filling the opening to form an insulating portion including a portion of the first insulator layer in the opening and a portion of the trench isolation structure below the portion of the first insulator layer in the opening.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate, sequentially forming a first protective layer and a second protective layer on the substrate;, etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column, removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column, removing a remaining portion of the second protective layer, and forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column. The first contact material layer in contact with the lower portion of the semiconductor column does not increase the source series resistance.

Abstract: A semiconductor device includes a substrate, a semiconductor column vertically disposed on the substrate, a first contact material layer on the substrate and in contact with a lower portion of the semiconductor column, a first insulating material layer on the first contact material layer and having an upper surface lower than an upper surface of the semiconductor column, a gate dielectric material layer on the first insulating material layer and on a portion of sidewalls of the semiconductor column while exposing an upper portion of the semiconductor column, and a gate stack structure on the gate dielectric material layer and surrounding a portion of the gate dielectric material layer on the sidewalls of the semiconductor column. The gate stack structure includes from inside to outside a P-type work function layer, an N-type work function layer, and a gate.

Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. This inventive concept reduces the loss of the interlayer dielectric layer, thus reduces the height loss of the gate electrode.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a semiconductor fin on a substrate, and a trench isolation structure surrounding the fin and having an upper surface flush with an upper surface of the fin and including first and second trench isolation portions on opposite sides of the fin along the fin longitudinal direction, and third and fourth trench isolation portions on distal ends of the fin along a second direction intersecting the longitudinal direction; forming a patterned first hardmask layer having an opening exposing an upper surface of the third and fourth trench isolation portions; and forming a first insulator layer filling the opening to form an insulating portion including a portion of the first insulator layer in the opening and a portion of the trench isolation structure below the portion of the first insulator layer in the opening.

Abstract: Methods and transistors for circuit structures are provided. The methods include, for instance: defining a channel region in a substrate, the channel region having at least one channel region sidewall adjoining an isolation material; recessing the isolation material to expose an upper portion of the at least one channel region sidewall; and providing a gate structure over a gate interface area with the channel region. The gate interface area includes at least the upper portion of the at least one channel region sidewall and an upper surface of the channel region so that a threshold voltage of the gate structure may be reduced. The methods may also include etching an elongate notch in the upper portion of the at least one channel region sidewall to increase a size of the gate interface area and further reduce the threshold voltage of the gate structure.

Abstract: Methods for preparing CMOS transistors having longer effective gate lengths and the resulting devices are disclosed. Embodiments include forming a dummy gate bound by spacers on opposing sides thereof, on a substrate; removing the dummy gate to form a trench between the spacers; modifying a gate channel portion of the substrate between the spacers to form inner or outer sidewalls; depositing a conformal high-k dielectric layer on the modified gate channel portion; and forming a metal gate in the trench.