Patents by Inventor Zhaoxuan Shen

Zhaoxuan Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11003827
    Abstract: Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed by one or more processors, cause the one or more processors to perform operations. The operations include: generating, using the one or more processors, a plurality of child processes according to a number of programmable dies of the multi-die device, each of the plurality of child processes corresponding to a respective programmable die of the multi-die device, wherein the plurality of child processes execute on different processors; partitioning a design for the multi-die device into a plurality of portions, each of the portions to be used to configure one of the programmable dies of the multi-die device; transmitting the plurality of portions of the design to the plurality of child processes for placement; and receiving placements from the plurality of child processes.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: May 11, 2021
    Assignee: XILINX, INC.
    Inventors: Paul D. Kundarewich, Grigor S. Gasparyan, Mehrdad Eslami Dehkordi, Guenter Stenz, Zhaoxuan Shen, Amish Pandya
  • Patent number: 6948138
    Abstract: A method for use by a placement and routing tool automatically selects positions for all n I/O buffers of an IC from among a set of m available legal positions for such buffers within an IC layout so as to best meet a set of criteria affected by I/O buffer placement. The method initially establishes a weighted cost function ci,j quantifying a cost, relative to that set of criteria, of assigning the ith I/O buffer to the jth legal position. The weighted cost function is then evaluated with respect to each possible combination of i and j to produce an m×n cost data matrix indicating all costs associated with all of the m×n possible I/O buffer placements. The cost data matrix is then analyzed to produce a placement plan assigning each I/O buffer to a separate legal position in a way that minimizes a total cost of the buffer placement with respect to the set of criteria. The method may also be used to assign I/O pads among a set of legal pad positions.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: September 20, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventor: Zhaoxuan Shen