Abstract: Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a tungsten (W) layer on the semiconductor substrate and depositing a molybdenum (Mo) layer on the tungsten (W) layer. In one method, a tungsten (W) capping layer is deposited on the molybdenum (Mo) layer, followed by formation of a nitride capping layer on the tungsten (W) capping layer). In a second method, a nitride capping layer is formed on the molybdenum (Mo) layer using an ammonia free process. Both processes result in the formation of a metal stack having low resistivity.

Abstract: Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a tungsten (W) layer on the semiconductor substrate and depositing a molybdenum (Mo) layer on the tungsten (W) layer. The tungsten (W) layer has a thickness in a range of from 5 ? to 30 ? and the molybdenum (Mo) layer has a thickness in a range of from 80 ? to 200 ?. In some embodiments, the metal stack has a resistivity of less than or equal to 10 ??-cm prior to treatment and a resistivity of less than or equal to 11 ??-cm after treatment when the metal stack has a total thickness of 140 ?.

Abstract: A method to produce a layered substrate includes depositing a ruthenium layer having a first average grain size on a substrate; annealing the substrate at a temperature and for a period of time sufficient to produce an annealed ruthenium layer having a second average grain size which is greater than the first average grain size; and removing a portion of the ruthenium layer by chemical mechanical planarization to form a planarized ruthenium layer, to produce the layered substrate. A layered substrate is also disclosed.

Abstract: A method to produce a layered substrate, which includes the steps of depositing a diffusion barrier layer on the substrate; depositing an underlayer comprising a Group 6 metal on the barrier layer; and depositing a ruthenium layer comprising ruthenium on the underlayer, to produce the layered substrate. A layered substrate is also disclosed.

Abstract: A catalyst structure includes: (1) a substrate; (2) a catalyst layer on the substrate; and (3) an adhesion layer disposed between the substrate and the catalyst layer. In some implementations, an average thickness of the adhesion layer is about 1 nm or less. In some implementations, a material of the catalyst layer at least partially extends into a region of the adhesion layer. In some implementations, the catalyst layer is characterized by a lattice strain imparted by the adhesion layer.

Abstract: A method to produce a layered substrate, which includes the steps of depositing a diffusion barrier layer on the substrate; depositing an underlayer comprising a Group 6 metal on the barrier layer; and depositing a ruthenium layer comprising ruthenium on the underlayer, to produce the layered substrate. A layered substrate is also disclosed.

Abstract: A catalyst structure includes: (1) a substrate; (2) a catalyst layer on the substrate; and (3) an adhesion layer disposed between the substrate and the catalyst layer. In some implementations, an average thickness of the adhesion layer is about 1 nm or less. In some implementations, a material of the catalyst layer at least partially extends into a region of the adhesion layer. In some implementations, the catalyst layer is characterized by a lattice strain imparted by the adhesion layer.

Abstract: A manufacturing process includes: depositing a first catalyst on a first gas diffusion layer (GDL) to form a first catalyst-coated GDL; depositing a first ionomer on the first catalyst-coated GDL to form a first gas diffusion electrode (GDE); depositing a second catalyst on a second GDL to form a second catalyst-coated GDL; depositing a second ionomer on the second catalyst-coated GDL to form a second GDE; and laminating the first GDE with the second GDE and with an electrolyte membrane disposed between the first GDE and the second GDE to form a membrane electrode assembly (MEA). A MEA includes a first GDL; a second GDL; an electrolyte membrane disposed between the first GDL and the second GDL; a first catalyst layer disposed between the first GDL and the electrolyte membrane; and a second catalyst layer disposed between the second GDL and the electrolyte membrane, wherein a thickness of the electrolyte membrane is about 15 ?m or less.

Abstract: A catalyst structure includes: (1) a substrate; (2) a catalyst layer on the substrate; and (3) an adhesion layer disposed between the substrate and the catalyst layer. In some implementations, an average thickness of the adhesion layer is about 1 nm or less. In some implementations, a material of the catalyst layer at least partially extends into a region of the adhesion layer. In some implementations, the catalyst layer is characterized by a lattice strain imparted by the adhesion layer.

Abstract: A manufacturing process includes: depositing a first catalyst on a first gas diffusion layer (GDL) to form a first catalyst-coated GDL; depositing a first ionomer on the first catalyst-coated GDL to form a first gas diffusion electrode (GDE); depositing a second catalyst on a second GDL to form a second catalyst-coated GDL; depositing a second ionomer on the second catalyst-coated GDL to form a second GDE; and laminating the first GDE with the second GDE and with an electrolyte membrane disposed between the first GDE and the second GDE to form a membrane electrode assembly (MEA). A MEA includes a first GDL; a second GDL; an electrolyte membrane disposed between the first GDL and the second GDL; a first catalyst layer disposed between the first GDL and the electrolyte membrane; and a second catalyst layer disposed between the second GDL and the electrolyte membrane, wherein a thickness of the electrolyte membrane is about 15 ?m or less.

Abstract: A manufacturing process includes: depositing a first catalyst on a first gas diffusion layer (GDL) to form a first catalyst-coated GDL; depositing a first ionomer on the first catalyst-coated GDL to form a first gas diffusion electrode (GDE); depositing a second catalyst on a second GDL to form a second catalyst-coated GDL; depositing a second ionomer on the second catalyst-coated GDL to form a second GDE; and laminating the first GDE with the second GDE and with an electrolyte membrane disposed between the first GDE and the second GDE to form a membrane electrode assembly (MEA). A MEA includes a first GDL; a second GDL; an electrolyte membrane disposed between the first GDL and the second GDL; a first catalyst layer disposed between the first GDL and the electrolyte membrane; and a second catalyst layer disposed between the second GDL and the electrolyte membrane, wherein a thickness of the electrolyte membrane is about 15 ?m or less.

Abstract: A catalyst structure includes: (1) a substrate; (2) a catalyst layer on the substrate; and (3) an adhesion layer disposed between the substrate and the catalyst layer. In some implementations, an average thickness of the adhesion layer is about 1 nm or less. In some implementations, a material of the catalyst layer at least partially extends into a region of the adhesion layer. In some implementations, the catalyst layer is characterized by a lattice strain imparted by the adhesion layer.