Abstract: The disclosure discloses a wafer acceptance test module for a static memory function test, reduced instruction built-in self-test circuit formed on a wafer includes: a ring oscillator, a frequency divider, a counter, a data latch and comparator. The counter is used for count, and the count is used as an input signal of each of an address decoder and a data input port at the same time. The data latch and comparator is connected to an output terminal of the address decoder and an output terminal of the sense amplifier and compare two output signals to obtain a test result. The disclosure also discloses a wafer acceptance test method for a static memory function test. The disclosure does not need to rely on a dedicated test machine for memory to perform a static memory function test, which can simplify a test procedure.

Abstract: The present disclosure relates to a circuit structure for in-memory computing. The circuit structure comprises a plurality of 8T SRAMs, four BLs, two WLs, and a direction configuration circuit. Each of the 8T SRAMs comprises two groups of read/write dual ports, two WL ports and two direction configuration ports. Data of first read/write port and second read/write port of each group of the read/write dual ports are inverse of each other. Each of the BLs is connected to a corresponding processor, and is connected to a read/write port of a corresponding read/write dual port of each 8T SRAM in a row direction or a column direction. Each of the WLs is connected to a corresponding processor and connected to a corresponding WL port of each 8T SRAM.

Abstract: The present disclosure relates to a circuit structure for in-memory computing. The circuit structure comprises a plurality of 8T SRAMs, four BLs, two WLs, and a direction configuration circuit. Each of the 8T SRAMs comprises two groups of read/write dual ports, two WL ports and two direction configuration ports. Data of first read/write port and second read/write port of each group of the read/write dual ports are inverse of each other. Each of the BLs is connected to a corresponding processor, and is connected to a read/write port of a corresponding read/write dual port of each 8T SRAM in a row direction or a column direction. Each of the WLs is connected to a corresponding processor and connected to a corresponding WL port of each 8T SRAM.

Abstract: The disclosure discloses a wafer acceptance test module for a static memory function test, reduced instruction built-in self-test circuit formed on a wafer includes: a ring oscillator, a frequency divider, a counter, a data latch and comparator. The counter is used for count, and the count is used as an input signal of each of an address decoder and a data input port at the same time. The data latch and comparator is connected to an output terminal of the address decoder and an output terminal of the sense amplifier and compare two output signals to obtain a test result. The disclosure also discloses a wafer acceptance test method for a static memory function test. The disclosure does not need to rely on a dedicated test machine for memory to perform a static memory function test, which can simplify a test procedure.