Abstract: a memory device includes an array of memory cells. Each memory cell includes a vertical transistor having a semiconductor body vertically extending in a first direction. Each memory cell includes a storage unit coupled to a first end of the semiconductor body and a bit line extending in a second direction perpendicular to the first direction. The bit line is connected to second ends of the semiconductor bodies of a row of the vertical transistors. The bit line includes a semiconductor epitaxial layer extending in the second direction and connected to the second ends of the semiconductor bodies of the row of the vertical transistors at a top surface of the semiconductor epitaxial layer.

Abstract: Implementations of the present application provide a semiconductor device, a fabrication method and a memory system. The semiconductor device includes a plurality of semiconductor pillars arranged in an array and a word line structure. The plurality of semiconductor pillars extend along a first direction and include at least one side face, wherein the plurality of semiconductor pillars are arranged in rows along a second direction perpendicular to the first direction. The word line structure is located between a first row and a second row of semiconductor pillars that are adjacent, and includes a first word line structure and a second word line structure spaced apart from the first word line structure, wherein the first word line structure is connected with a side face of the first row of semiconductor pillars, and the second word line structure is connected with a side face of the second row of semiconductor pillars.

Abstract: Systems, devices, and methods for managing vertical structures in three-dimensional (3D) semiconductor devices are provided. In one aspect, a method includes: providing a semiconductor substrate, and forming isolating regions between a plurality of adjacent vertical transistors in the semiconductor substrate. Each vertical transistor of the plurality of adjacent vertical transistors extends along a vertical direction. Two adjacent vertical transistors and a corresponding isolating region between the two adjacent vertical transistors are positioned along a horizontal direction perpendicular to the vertical direction. The corresponding isolating region includes a conductive material, and, along the vertical direction, a length of the conductive material in the corresponding isolating region is greater than a length of a vertical gate of each of the two adjacent vertical transistors.

Abstract: Systems, devices, and methods for managing three-dimensional semiconductor devices are provided. In one aspect, a method includes: forming strings of memory cells in a first side of a semiconductor substrate having a semiconductor material, forming alternating stripes of the semiconductor material and an isolating material in a second, opposite side of the semiconductor substrate, and forming bit lines in the second side of the semiconductor substrate. The bit lines can be formed by depositing a layer of a metallic material on the alternating stripes of the semiconductor material and the isolating material, and forming each bit line of the bit lines in a corresponding stripe of the semiconductor material of the alternating stripes by forming a composite conductive material based on the metallic material and the semiconductor material in the corresponding stripe of the semiconductor material.

Abstract: Semiconductor structures, fabrication methods thereof, and memory systems are provided. In one aspect, a method of forming a semiconductor structure includes: forming a plurality of first trenches in a semiconductor base from a surface of the semiconductor base, forming a plurality of gate structures in the plurality of first trenches, forming a plurality of second trenches in the semiconductor base, and forming a plurality of isolation structures in the plurality of second trenches. The plurality of first trenches extend along a first direction. Each of the plurality of second trenches is between two adjacent trenches of the plurality of first trenches, and the plurality of second trenches extend along the first direction.

Abstract: The present application discloses a semiconductor device and a fabrication method thereof, and a memory system. The device includes a plurality of semiconductor pillars extending in a third direction, and a plurality of gate structures and shielding structures extending along a first direction. The gate structures and the shielding structures are in a staggered distribution along a second direction, and the semiconductor pillars are located between the shielding structures and the gate structures that are adjacent. Sizes of the gate structures along the first direction are smaller than sizes of the shielding structures along the first direction, and orthographic projections of the gate structures are within ranges of orthographic projections of the shielding structures along the second direction.

Abstract: Examples of the present application provide a semiconductor device, a memory system and a fabrication method of a semiconductor device. The semiconductor device includes: a silicon contact structure; a metal silicide layer on one side of the silicon contact structure; a bit line structure located on the side of the metal silicide layer away from the silicon contact structure and extending in a first direction; and a sidewall structure covering the opposite sides of the bit line structure and the opposite sides of the metal silicide layer in the first direction and extending further to cover the opposite sides, in the first direction, of the first end of the silicon contact structure proximate to the metal silicide layer.

Abstract: The present disclosure discloses a memory device, a method for fabricating a memory device, and a memory system. The method includes: forming a plurality of semiconductor bodies spaced apart and forming spacing portions between adjacent semiconductor bodies, where the plurality of semiconductor bodies extend along a first direction; removing part of the plurality of semiconductor bodies to form a plurality of first grooves between adjacent first spacing portions; forming mask portions protruding out from the first grooves within the first grooves, to form second grooves between adjacent mask portions; forming spacer portions within the second grooves and removing the mask portions to form third grooves between adjacent second spacer portions; and forming conductive connection portions connected to the semiconductor bodies along the first direction within the third grooves.

Abstract: Examples include forming first trenches extending along a first direction on a first side of a semiconductor layer, and forming an insulation layer within the first trenches; forming second trenches extending along a second direction on the first side, the depths of the second trenches less than depths of the first trenches, the first and second directions intersecting; forming a first gate insulation layer and first gate conductive layer sequentially on inner walls of the second trenches; removing part of the semiconductor layer, part of the insulation layer and part of the first gate insulation layer from a second side of the semiconductor layer facing away from the first side, to expose the first gate conductive layer; and removing a part of the first gate conductive layer from the second side, to divide the first gate conductive layer into first gates located on opposite sidewalls of the second trenches respectively.

Abstract: Examples of the present application disclose a semiconductor device and a fabrication method of the semiconductor device, a memory and a memory system. The method comprises: providing a substrate; forming a stop layer on a side of the substrate; forming a semiconductor layer on a side of the stop layer facing away from the substrate; forming first through-holes penetrating through the semiconductor layer and the stop layer; and forming gate structures on part of inner walls and part of bottoms of the first through-holes.

Abstract: The present disclosure relates to a piezoelectric structure with an optimized electromechanical coupling coefficient, a method for manufacturing the piezoelectric structure, and a piezoelectric resonator including the piezoelectric structure. The piezoelectric structure according to the present disclosure may include a piezoelectric layer doped with a first doping element at a first doping concentration. The first doping concentration varies along a thickness direction of the piezoelectric layer with at least two change rates. An electromechanical coupling coefficient of the piezoelectric layer continuously varies along the thickness direction of the piezoelectric layer.

Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.

Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.

Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.

Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.

Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.

Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.

Abstract: The present disclosure provides a semiconductor device, comprising: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an hollow cavity below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer. Such a device structure of the present disclosure incorporate the respective advantages of the bulk silicon device and the SOI device, and has characteristics of lower cost, smaller leakage current, lower power consumption, fast speed, simple process and high integration level. Meanwhile, the floating body effect and the spontaneous heating effect are eliminated as compared with the SOI device.

Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.

Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.