Patents by Inventor Zhaoyun TANG
Zhaoyun TANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11404442Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.Type: GrantFiled: July 2, 2020Date of Patent: August 2, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zongliang Huo, Wenbin Zhou, Zhiguo Zhao, Zhaoyun Tang, Hai Lin Xiong
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Publication number: 20200335521Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.Type: ApplicationFiled: July 2, 2020Publication date: October 22, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zongliang HUO, Wenbin ZHOU, Zhiguo ZHAO, Zhaoyun TANG, Hai Lin XIONG
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Patent number: 10756113Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.Type: GrantFiled: October 22, 2018Date of Patent: August 25, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zongliang Huo, Wenbin Zhou, Zhiguo Zhao, Zhaoyun Tang, Hai Lin Xiong
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Patent number: 10734397Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.Type: GrantFiled: September 10, 2018Date of Patent: August 4, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Cheng Zhou, Bin Yuan, QingBo Liu, Song Man Xu, Siying Liu, Rui Gong, Zhiguo Zhao, Zhaoyun Tang, Zhiliang Xia, Zongliang Huo
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Publication number: 20190157298Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.Type: ApplicationFiled: October 22, 2018Publication date: May 23, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zongliang Huo, Wenbin Zhou, Zhiguo Zhao, Zhaoyun Tang, Hai Lin Xiong
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Publication number: 20190081055Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.Type: ApplicationFiled: September 10, 2018Publication date: March 14, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Cheng ZHOU, Bin Yuan, QingBo Liu, Song Man Xu, Siying Liu, Rui Gong, Zhiguo Zhao, Zhaoyun Tang, Zhiliang Xia, Zongliang Huo
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Publication number: 20160293695Abstract: The present disclosure provides a semiconductor device, comprising: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an hollow cavity below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer. Such a device structure of the present disclosure incorporate the respective advantages of the bulk silicon device and the SOI device, and has characteristics of lower cost, smaller leakage current, lower power consumption, fast speed, simple process and high integration level. Meanwhile, the floating body effect and the spontaneous heating effect are eliminated as compared with the SOI device.Type: ApplicationFiled: August 15, 2014Publication date: October 6, 2016Inventors: Jing Xu, Jiang Yan, Bangming Chen, Hongli Wang, Bo Tang, Zhaoyun Tang, Yefeng Xu, Chunlong Li, Mengmeng Yang
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Patent number: 9306003Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.Type: GrantFiled: August 15, 2014Date of Patent: April 5, 2016Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Jing Xu, Jiang Yan, Bangming Chen, Hongli Wang, Bo Tang, Zhaoyun Tang, Yefeng Xu, Chunlong Li, Mengmeng Yang
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Publication number: 20160020274Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.Type: ApplicationFiled: August 15, 2014Publication date: January 21, 2016Inventors: Jing Xu, Jiang Yan, Bangming Chen, Hongli Wang, Bo Tang, Zhaoyun Tang, Yefeng Xu, Chunlong Li, Mengmeng Yang
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Publication number: 20150340464Abstract: A semiconductor device manufacturing method includes forming a gate opening in a semiconductor layer; forming a sacrificial gate in the gate opening; forming a source region and a drain region in the semiconductor layer in proximity to the gate opening; removing the sacrificial gate; and forming a gate stack comprising a replacement gate dielectric layer and a replacement gate conductor layer in the gate opening, wherein the gate opening is configured to define a thickness of a portion of the semiconductor layer for a channel region. Channel control in semiconductor devices formed according to the above method can be effectively improved.Type: ApplicationFiled: July 30, 2015Publication date: November 26, 2015Inventors: Zhaoyun TANG, Jiang YAN