Patents by Inventor Zhaoyun TANG

Zhaoyun TANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200335521
    Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zongliang HUO, Wenbin ZHOU, Zhiguo ZHAO, Zhaoyun TANG, Hai Lin XIONG
  • Patent number: 10756113
    Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 25, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zongliang Huo, Wenbin Zhou, Zhiguo Zhao, Zhaoyun Tang, Hai Lin Xiong
  • Patent number: 10734397
    Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 4, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Cheng Zhou, Bin Yuan, QingBo Liu, Song Man Xu, Siying Liu, Rui Gong, Zhiguo Zhao, Zhaoyun Tang, Zhiliang Xia, Zongliang Huo
  • Publication number: 20190157298
    Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.
    Type: Application
    Filed: October 22, 2018
    Publication date: May 23, 2019
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zongliang Huo, Wenbin Zhou, Zhiguo Zhao, Zhaoyun Tang, Hai Lin Xiong
  • Publication number: 20190081055
    Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 14, 2019
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Cheng ZHOU, Bin Yuan, QingBo Liu, Song Man Xu, Siying Liu, Rui Gong, Zhiguo Zhao, Zhaoyun Tang, Zhiliang Xia, Zongliang Huo
  • Publication number: 20160293695
    Abstract: The present disclosure provides a semiconductor device, comprising: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an hollow cavity below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer. Such a device structure of the present disclosure incorporate the respective advantages of the bulk silicon device and the SOI device, and has characteristics of lower cost, smaller leakage current, lower power consumption, fast speed, simple process and high integration level. Meanwhile, the floating body effect and the spontaneous heating effect are eliminated as compared with the SOI device.
    Type: Application
    Filed: August 15, 2014
    Publication date: October 6, 2016
    Inventors: Jing Xu, Jiang Yan, Bangming Chen, Hongli Wang, Bo Tang, Zhaoyun Tang, Yefeng Xu, Chunlong Li, Mengmeng Yang
  • Patent number: 9306003
    Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: April 5, 2016
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Jing Xu, Jiang Yan, Bangming Chen, Hongli Wang, Bo Tang, Zhaoyun Tang, Yefeng Xu, Chunlong Li, Mengmeng Yang
  • Publication number: 20160020274
    Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.
    Type: Application
    Filed: August 15, 2014
    Publication date: January 21, 2016
    Inventors: Jing Xu, Jiang Yan, Bangming Chen, Hongli Wang, Bo Tang, Zhaoyun Tang, Yefeng Xu, Chunlong Li, Mengmeng Yang
  • Publication number: 20150340464
    Abstract: A semiconductor device manufacturing method includes forming a gate opening in a semiconductor layer; forming a sacrificial gate in the gate opening; forming a source region and a drain region in the semiconductor layer in proximity to the gate opening; removing the sacrificial gate; and forming a gate stack comprising a replacement gate dielectric layer and a replacement gate conductor layer in the gate opening, wherein the gate opening is configured to define a thickness of a portion of the semiconductor layer for a channel region. Channel control in semiconductor devices formed according to the above method can be effectively improved.
    Type: Application
    Filed: July 30, 2015
    Publication date: November 26, 2015
    Inventors: Zhaoyun TANG, Jiang YAN