Patents by Inventor Zhe Ge

Zhe Ge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10475780
    Abstract: A method for configuring level shifter spare cells includes providing a power rail connectable to a corresponding power domain, and providing a spare cell including a level shifter circuit. The level shifter circuit has first and second terminals that are connectable to the power rail, and the first and second terminals are floating with respect to the power rail.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: November 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Zhe Ge, Miaolin Tan, Peidong Wang
  • Publication number: 20190140642
    Abstract: An isolation cell clamps a signal passing from a first, powered-down power domain to a second, power-on power domain. To reduce leakage current, some of the circuits and devices are connected to a voltage supply of the first or “from” power domain, while other circuits and devices are connected to a voltage supply of the second or “to” power domain.
    Type: Application
    Filed: March 15, 2018
    Publication date: May 9, 2019
    Inventors: PEIDONG WANG, Miaolin Tan, Zhe Ge
  • Patent number: 10263619
    Abstract: An isolation cell clamps a signal passing from a first, powered-down power domain to a second, power-on power domain. To reduce leakage current, some of the circuits and devices are connected to a voltage supply of the first or “from” power domain, while other circuits and devices are connected to a voltage supply of the second or “to” power domain.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 16, 2019
    Assignee: NXP USA, INC.
    Inventors: Peidong Wang, Miaolin Tan, Zhe Ge
  • Publication number: 20190067263
    Abstract: A method for configuring level shifter spare cells includes providing a power rail connectable to a corresponding power domain, and providing a spare cell including a level shifter circuit. The level shifter circuit has first and second terminals that are connectable to the power rail, and the first and second terminals are floating with respect to the power rail.
    Type: Application
    Filed: September 14, 2017
    Publication date: February 28, 2019
    Inventors: Zhe Ge, Miaolin Tan, Peidong Wang
  • Patent number: 9838013
    Abstract: A multi-bit clock gating cell is used in an integrated circuit (IC) in place of single bit clock gating cells to reduce power consumption. A physical design method is used to form a clock tree of the IC. Initial positions of clock gating cells are defined with respective initial clock input paths. Selected clock gating cells are moved to modified positions in which they may be adjoining. Adjoining cells are merged by substituting a multi-bit clock gating cell having multiple gating signal inputs, corresponding gated clock outputs, and a common clock input path. A net reduction is obtained for the overall capacitance of the clock path due to reduction of the upstream capacitance of the clock path and of the resulting multi-bit clock gating cell itself, compared with the aggregate capacitance of the clock paths of the corresponding clock gating cells before moving and merging.
    Type: Grant
    Filed: November 20, 2016
    Date of Patent: December 5, 2017
    Assignee: NXP USA, INC.
    Inventors: Zhe Ge, Huabin Du, Miaolin Tan, Peidong Wang
  • Publication number: 20170302277
    Abstract: A multi-bit clock gating cell is used in an integrated circuit (IC) in place of single bit clock gating cells to reduce power consumption. A physical design method is used to form a clock tree of the IC. Initial positions of clock gating cells are defined with respective initial clock input paths. Selected clock gating cells are moved to modified positions in which they may be adjoining. Adjoining cells are merged by substituting a multi-bit clock gating cell having multiple gating signal inputs, corresponding gated clock outputs, and a common clock input path. A net reduction is obtained for the overall capacitance of the clock path due to reduction of the upstream capacitance of the clock path and of the resulting multi-bit clock gating cell itself, compared with the aggregate capacitance of the clock paths of the corresponding clock gating cells before moving and merging.
    Type: Application
    Filed: November 20, 2016
    Publication date: October 19, 2017
    Inventors: Zhe Ge, Huabin Du, Miaolin Tan, Peidong Wang
  • Patent number: 9553581
    Abstract: A multi-module integrated circuit (IC) can be configured in different types of packages having different modules enabled or disabled. A module that can be disabled has driven circuitry that is known a priori to have a low-power input vector that places the driven circuitry into a low leakage power state. The module also has driving circuitry with one or more package-aware cells. The IC has a package-aware controller that generates control signals for the package-aware cells that ensure that the outputs from the package-aware cells are forced to particular values (i.e., either logical-0 or logical-1) that cause the low power input vector to be applied to the driven circuitry when the IC is assembled in a package in which the module is disabled. In this way, module leakage power is reduced for package types in which certain modules are disabled.
    Type: Grant
    Filed: November 1, 2015
    Date of Patent: January 24, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhe Ge, Zhiwei Lu, Miaolin Tan
  • Publication number: 20160329895
    Abstract: A multi-module integrated circuit (IC) can be configured in different types of packages having different modules enabled or disabled. A module that can be disabled has driven circuitry that is known a priori to have a low-power input vector that places the driven circuitry into a low leakage power state. The module also has driving circuitry with one or more package-aware cells. The IC has a package-aware controller that generates control signals for the package-aware cells that ensure that the outputs from the package-aware cells are forced to particular values (i.e., either logical-0 or logical-1) that cause the low power input vector to be applied to the driven circuitry when the IC is assembled in a package in which the module is disabled. In this way, module leakage power is reduced for package types in which certain modules are disabled.
    Type: Application
    Filed: November 1, 2015
    Publication date: November 10, 2016
    Inventors: Zhe Ge, Zhiwei Lu, Miaolin Tan