Patents by Inventor Zhe Ge
Zhe Ge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120144Abstract: A high-frequency transformer, includes: an iron core, primary windings and secondary windings, wherein the iron core is of an integrated equilateral triangle structure, the primary windings and the secondary windings are uniformly wound around three sides of the iron core, and the primary windings and/or the secondary windings are symmetrically distributed on the three sides.Type: ApplicationFiled: August 28, 2018Publication date: April 11, 2024Applicants: GLOBAL ENERGY INTERCONNECTION RESEARCH INSTITUTE CO., LTD., STATE GRID CORPORATION OF CHINA, State Grid Shanghai Electric Power Co. LtdInventors: Zhanfeng DENG, Guoliang ZHAO, Jun GE, Guangyao QIAO, Xiaolin MO, Dong LIANG, Zhe ZHOU
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Patent number: 11955071Abstract: A pixel circuit, a display panel and a method for driving the pixel circuit. The pixel circuit includes a first light emission control module and a gate initialization module. The first light emission control module includes a control terminal, a first terminal and a second terminal, where the control terminal of the first light emission control module is electrically connected with a first light emission control signal, the first terminal of the first light emission control module is electrically connected with a first power signal, and the second terminal of the first light emission control module is electrically connected to the first electrode of the drive transistor.Type: GrantFiled: March 10, 2022Date of Patent: April 9, 2024Assignee: KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTDInventors: Dongfang Zhao, Zhe Du, Junfeng Li, Gang Wang, Yong Ge
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Patent number: 11929368Abstract: An array substrate and a display panel. The array substrate includes a thin film transistor array layer including a driving transistor, a switching transistor, and a capacitor. The driving transistor includes a first active layer, a first gate insulating layer, a first gate, and an insulating dielectric layer sequentially stacked. The switching transistor includes a second active layer, a second gate insulating layer, and a second gate sequentially stacked. The insulating dielectric layer and the second gate insulating layer are located at a same layer. A thickness of the first gate insulating layer is greater than a thickness of the second gate insulating layer. The capacitor includes a first electrode plate and a second electrode plate. The first electrode plate and the first gate are disposed on same layer, and the second electrode plate and the second gate are disposed on same layer.Type: GrantFiled: November 4, 2021Date of Patent: March 12, 2024Assignee: Yungu (Gu'an) Technology Co., Ltd.Inventors: Dongfang Zhao, Kookchul Moon, Junfeng Li, Zhe Du, Yong Ge, Sha Yuan, Lin Xu
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Patent number: 10475780Abstract: A method for configuring level shifter spare cells includes providing a power rail connectable to a corresponding power domain, and providing a spare cell including a level shifter circuit. The level shifter circuit has first and second terminals that are connectable to the power rail, and the first and second terminals are floating with respect to the power rail.Type: GrantFiled: September 14, 2017Date of Patent: November 12, 2019Assignee: NXP USA, Inc.Inventors: Zhe Ge, Miaolin Tan, Peidong Wang
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Publication number: 20190140642Abstract: An isolation cell clamps a signal passing from a first, powered-down power domain to a second, power-on power domain. To reduce leakage current, some of the circuits and devices are connected to a voltage supply of the first or “from” power domain, while other circuits and devices are connected to a voltage supply of the second or “to” power domain.Type: ApplicationFiled: March 15, 2018Publication date: May 9, 2019Inventors: PEIDONG WANG, Miaolin Tan, Zhe Ge
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Patent number: 10263619Abstract: An isolation cell clamps a signal passing from a first, powered-down power domain to a second, power-on power domain. To reduce leakage current, some of the circuits and devices are connected to a voltage supply of the first or “from” power domain, while other circuits and devices are connected to a voltage supply of the second or “to” power domain.Type: GrantFiled: March 15, 2018Date of Patent: April 16, 2019Assignee: NXP USA, INC.Inventors: Peidong Wang, Miaolin Tan, Zhe Ge
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Publication number: 20190067263Abstract: A method for configuring level shifter spare cells includes providing a power rail connectable to a corresponding power domain, and providing a spare cell including a level shifter circuit. The level shifter circuit has first and second terminals that are connectable to the power rail, and the first and second terminals are floating with respect to the power rail.Type: ApplicationFiled: September 14, 2017Publication date: February 28, 2019Inventors: Zhe Ge, Miaolin Tan, Peidong Wang
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Patent number: 9838013Abstract: A multi-bit clock gating cell is used in an integrated circuit (IC) in place of single bit clock gating cells to reduce power consumption. A physical design method is used to form a clock tree of the IC. Initial positions of clock gating cells are defined with respective initial clock input paths. Selected clock gating cells are moved to modified positions in which they may be adjoining. Adjoining cells are merged by substituting a multi-bit clock gating cell having multiple gating signal inputs, corresponding gated clock outputs, and a common clock input path. A net reduction is obtained for the overall capacitance of the clock path due to reduction of the upstream capacitance of the clock path and of the resulting multi-bit clock gating cell itself, compared with the aggregate capacitance of the clock paths of the corresponding clock gating cells before moving and merging.Type: GrantFiled: November 20, 2016Date of Patent: December 5, 2017Assignee: NXP USA, INC.Inventors: Zhe Ge, Huabin Du, Miaolin Tan, Peidong Wang
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Publication number: 20170302277Abstract: A multi-bit clock gating cell is used in an integrated circuit (IC) in place of single bit clock gating cells to reduce power consumption. A physical design method is used to form a clock tree of the IC. Initial positions of clock gating cells are defined with respective initial clock input paths. Selected clock gating cells are moved to modified positions in which they may be adjoining. Adjoining cells are merged by substituting a multi-bit clock gating cell having multiple gating signal inputs, corresponding gated clock outputs, and a common clock input path. A net reduction is obtained for the overall capacitance of the clock path due to reduction of the upstream capacitance of the clock path and of the resulting multi-bit clock gating cell itself, compared with the aggregate capacitance of the clock paths of the corresponding clock gating cells before moving and merging.Type: ApplicationFiled: November 20, 2016Publication date: October 19, 2017Inventors: Zhe Ge, Huabin Du, Miaolin Tan, Peidong Wang
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Patent number: 9553581Abstract: A multi-module integrated circuit (IC) can be configured in different types of packages having different modules enabled or disabled. A module that can be disabled has driven circuitry that is known a priori to have a low-power input vector that places the driven circuitry into a low leakage power state. The module also has driving circuitry with one or more package-aware cells. The IC has a package-aware controller that generates control signals for the package-aware cells that ensure that the outputs from the package-aware cells are forced to particular values (i.e., either logical-0 or logical-1) that cause the low power input vector to be applied to the driven circuitry when the IC is assembled in a package in which the module is disabled. In this way, module leakage power is reduced for package types in which certain modules are disabled.Type: GrantFiled: November 1, 2015Date of Patent: January 24, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Zhe Ge, Zhiwei Lu, Miaolin Tan
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Publication number: 20160329895Abstract: A multi-module integrated circuit (IC) can be configured in different types of packages having different modules enabled or disabled. A module that can be disabled has driven circuitry that is known a priori to have a low-power input vector that places the driven circuitry into a low leakage power state. The module also has driving circuitry with one or more package-aware cells. The IC has a package-aware controller that generates control signals for the package-aware cells that ensure that the outputs from the package-aware cells are forced to particular values (i.e., either logical-0 or logical-1) that cause the low power input vector to be applied to the driven circuitry when the IC is assembled in a package in which the module is disabled. In this way, module leakage power is reduced for package types in which certain modules are disabled.Type: ApplicationFiled: November 1, 2015Publication date: November 10, 2016Inventors: Zhe Ge, Zhiwei Lu, Miaolin Tan