Patents by Inventor Zhe-Hao Zhang
Zhe-Hao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200035832Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: ApplicationFiled: October 7, 2019Publication date: January 30, 2020Inventors: Cheng-Yen YU, Che-Cheng CHANG, Tung-Wen CHENG, Zhe-Hao ZHANG, Bo-Feng YOUNG
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Patent number: 10546956Abstract: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.Type: GrantFiled: December 21, 2018Date of Patent: January 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang
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Patent number: 10483394Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: GrantFiled: August 6, 2018Date of Patent: November 19, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
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Publication number: 20190319128Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.Type: ApplicationFiled: June 25, 2019Publication date: October 17, 2019Inventors: CHE-CHENG CHANG, TUNG-WEN CHENG, ZHE-HAO ZHANG, YUNG JUNG CHANG
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Patent number: 10340382Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.Type: GrantFiled: December 26, 2017Date of Patent: July 2, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Che-Cheng Chang, Tung-Wen Cheng, Yung Jung Chang, Zhe-Hao Zhang
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Publication number: 20190123168Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Inventors: Bo-Feng Young, Che-Cheng Chang, Mu-Tsang Lin, Tung-Wen Cheng, Zhe-Hao Zhang
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Publication number: 20190123205Abstract: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang
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Publication number: 20190115473Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.Type: ApplicationFiled: December 21, 2018Publication date: April 18, 2019Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Yung-Jung Chang
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Patent number: 10164109Abstract: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.Type: GrantFiled: January 29, 2015Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang
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Patent number: 10164050Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.Type: GrantFiled: July 16, 2015Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Feng Young, Che-Cheng Chang, Mu-Tsang Lin, Tung-Wen Cheng, Zhe-Hao Zhang
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Patent number: 10164108Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.Type: GrantFiled: October 17, 2014Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Yung-Jung Chang
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Publication number: 20180342619Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: ApplicationFiled: August 6, 2018Publication date: November 29, 2018Inventors: Cheng-Yen YU, Che-Cheng CHANG, Tung-Wen CHENG, Zhe-Hao ZHANG, Bo-Feng YOUNG
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Patent number: 10084060Abstract: The present disclosure provide a semiconductor structure, including a substrate having a top surface; a gate over the substrate, the gate including a footing region in proximity to the top surface, the footing region including a footing length laterally measured at a height under 10 nm above the top surface; and a spacer surrounding a sidewall of the gate, including a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface. The footing length is measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between a gate body and the spacer, and the spacer width is substantially equal to or greater than the footing length.Type: GrantFiled: August 15, 2014Date of Patent: September 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Kuo Hui Chang, Che-Cheng Chang, Mu-Tsang Lin
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Patent number: 10043906Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: GrantFiled: January 10, 2017Date of Patent: August 7, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
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Publication number: 20180145173Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.Type: ApplicationFiled: December 26, 2017Publication date: May 24, 2018Inventors: CHE-CHENG CHANG, TUNG-WEN CHENG, YUNG JUNG CHANG, ZHE-HAO ZHANG
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Patent number: 9853154Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.Type: GrantFiled: August 1, 2014Date of Patent: December 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Yung Jung Chang
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Patent number: 9799771Abstract: Methods for manufacturing a FinFET and a FinFET are provided. In various embodiments, the method for manufacturing a FinFET includes etching a base substrate to form a trapezoidal fin structure. Next, an isolation layer is deposited covering the etched base substrate. Then, the trapezoidal fin structure is exposed. The trapezoidal fin structure includes a top surface and a bottom surface, and the top surface has a width larger than that of the bottom surface.Type: GrantFiled: April 20, 2015Date of Patent: October 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tung-Wen Cheng, Che-Cheng Chang, Mu-Tsang Lin, Zhe-Hao Zhang
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Patent number: 9799103Abstract: An image processing method is applied to an electrical device. The image processing method includes the following steps: reading a first image; defining a motion blur center-point on the first image; receiving a dragging track executed on the first image; and executing a motion blur process according to the motion blur center-point and the dragging track to generate a second image. A motion blur level and a motion blur type of the second image are determined according to a related parameter between the dragging track and the motion blur center-point.Type: GrantFiled: September 6, 2016Date of Patent: October 24, 2017Assignee: ASUSTEK COMPUTER INC.Inventor: Zhe-Hao Zhang
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Publication number: 20170250286Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Yung-Jung Chang
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Patent number: 9653605Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.Type: GrantFiled: October 17, 2014Date of Patent: May 16, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Yung-Jung Chang