Abstract: A medical image diagnostic apparatus according to an embodiment includes processing circuitry. The medical image diagnostic apparatus performs image registration between medical image data. The processing circuitry extracts a structure of the subject included in the medical image data. The processing circuitry sets a display scale of the subject to a specified value. The processing circuitry performs image registration between the medical image data on the display scale of the specified value.

Abstract: An ultrasound diagnostic apparatus includes processing circuitry. The processing circuitry generates a first image based on an echo signal obtained by transmission and reception of ultrasound waves. The processing circuitry acquires a second image that is an image generated by a medical image diagnostic apparatus. The processing circuitry performs a registration of the first image and the second image, by discretely setting a plurality of relative positions of the first image and the second image within a specified range, calculating the similarity between the first image and the second image corresponding to the plurality of relative positions respectively, updating the plurality of the relative positions based on the calculation result of the similarity, and recalculating the similarity corresponding to the plurality of the updated relative positions respectively. The processing circuitry causes a display to display the images obtained after the registration.

Abstract: A medical image diagnostic apparatus according to an embodiment includes processing circuitry configured to determine a plurality of small blocks for each of a plurality of pieces of medical image data, generate a plurality of superpixels corresponding to the plurality of small blocks, assign a label to at least one of the plurality of pieces of medical image data, and perform registration between the plurality of pieces of medical image data using the plurality of superpixels and the label.

Abstract: An ultrasound diagnosis apparatus according to an embodiment includes processing circuitry. The processing circuitry acquires a plurality of frames representing ultrasound images starting with an initial frame in time series. The processing circuitry compares a current frame and a previous frame to the current frame for determining the similarity therebetween, and generates a reference frame based on weighting processing on the initial frame and the previous frame using results of the comparison. The processing circuitry implements tracking processing between the reference frame and the current frame.

Abstract: An ultrasound diagnosis apparatus according to an embodiment includes processing circuitry. The processing circuitry acquires a plurality of frames representing ultrasound images starting with an initial frame in time series. The processing circuitry compares a current frame and a previous frame to the current frame for determining the similarity therebetween, and generates a reference frame based on weighting processing on the initial frame and the previous frame using results of the comparison. The processing circuitry implements tracking processing between the reference frame and the current frame.

Abstract: A device and methods for forming a device are disclosed. The device includes a substrate having first, second and third regions. The first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region. A memory cell which includes a memory transistor having a first stack height (TSM) is disposed in the first region. A high voltage (HV) transistor having a second stack height (TSHV) is disposed in the second region and a logic transistor having a third stack height (TSL) is disposed in the third region. The first, second and third stack heights are substantially the same across the substrate.

Abstract: A device and methods for forming a device are disclosed. The device includes a substrate having first, second and third regions. The first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region. A memory cell which includes a memory transistor having a first stack height (TSM) is disposed in the first region. A high voltage (HV) transistor having a second stack height (TSHV) is disposed in the second region and a logic transistor having a third stack height (TSL) is disposed in the third region. The first, second and third stack heights are substantially the same across the substrate.

Abstract: An approach for utilizing electrical capacitance between a plurality of contacts and sidewalls to provide voltage coupling between a floating gate (FG) and a control gate (CG) is disclosed. Embodiments include providing an FG and a CG laterally separated from each other; coupling a plurality of parallel polysilicon lines to the FG; providing a plurality of contacts between the plurality of the parallel polysilicon lines and coupling the contacts to the CG; and forming an electrical capacitance between the plurality of contacts and sidewalls of the plurality of parallel polysilicon lines to provide voltage coupling between the CG and the FG.