Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.

Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.

Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

Abstract: A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.

Abstract: A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.

Abstract: A method of forming a layout design is disclosed. The method includes placing a first set of layout patterns in a first layout layer and placing a second set of layout patterns in a second layout layer. The first set of layout patterns is aligned with one or more grid lines of a first set of grid lines. The first set of grid lines extends along a first direction, where two grid lines of the first set of grid lines overlap two cell boundaries of a standard cell layout. The second set of layout patterns is aligned with one or more grid lines of a second set of grid lines. The second set of grid lines extends along the first direction and has at least two different line pitches, where two grid lines of the second set of grid lines overlap two cell boundaries of the standard cell layout.

Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns. K is an integer equal to or greater than two, and k is an order index ranging from 1 to K. The region of the layout design is sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality.

Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns. K is an integer equal to or greater than two, and k is an order index ranging from 1 to K. The region of the layout design is sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality.

Abstract: A method of forming a layout design is disclosed. The method includes placing a first set of layout patterns in a first layout layer and placing a second set of layout patterns in a second layout layer. The first set of layout patterns is aligned with one or more grid lines of a first set of grid lines. The first set of grid lines extends along a first direction, where two grid lines of the first set of grid lines overlap two cell boundaries of a standard cell layout. The second set of layout patterns is aligned with one or more grid lines of a second set of grid lines. The second set of grid lines extends along the first direction and has at least two different line pitches, where two grid lines of the second set of grid lines overlap two cell boundaries of the standard cell layout.

Abstract: A system and method of producing an integrated circuit using abutted cells having shared polycrystalline silicon on an oxide definition region edge (PODE) includes modeling inter-cell leakage current in a plurality of different cells. Each of the plurality of different cells is abutted with another cell and having the shared PODE. The method also comprises verifying a pre-determined acceptable power consumption of the integrated circuit based on the inter-cell leakage current.

Abstract: A system and method of producing an integrated circuit using abutted cells having shared polycrystalline silicon on an oxide definition region edge (PODE) includes modeling inter-cell leakage current in a plurality of different cells. Each of the plurality of different cells is abutted with another cell and having the shared PODE. The method also comprises verifying a pre-determined acceptable power consumption of the integrated circuit based on the inter-cell leakage current.

Abstract: A method including developing a circuit schematic diagram, the circuit schematic diagram including a plurality of cells. The method further includes generating cell placement rules for the plurality of cells based on the circuit schematic diagram and developing a circuit layout diagram for the plurality of cells based on the cell placement rules. The method further includes grouping the plurality of cells of the circuit layout diagram based on threshold voltages and inserting threshold voltage compliant fillers into the circuit layout diagram. A system for implementing the method is described. A layout formed by the method is also described.

Abstract: A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.

Abstract: A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.

Abstract: A method includes selecting a cell stored in a non-transient computer readable storage medium, arranging a plurality of the cells on a model of a semiconductor device, and creating a mask for the semiconductor device based on the model of the semiconductor device. The cell is designed according to a design rule in which a first power-supply-connection via satisfies a criterion from the group consisting of: i) the first power-supply-connection via is spaced apart from a second power-supply-connection via by a distance that is greater than a threshold distance such that the cell can be fabricated by a single-photolithography single-etch process, or ii) the first power-supply-connection via is coupled to first and second substantially parallel conductive lines that extend along directly adjacent tracks.

Abstract: A method includes selecting a cell stored in a non-transient computer readable storage medium, arranging a plurality of the cells on a model of a semiconductor device, and creating a mask for the semiconductor device based on the model of the semiconductor device. The cell is designed according to a design rule in which a first power-supply-connection via satisfies a criterion from the group consisting of: i) the first power-supply-connection via is spaced apart from a second power-supply-connection via by a distance that is greater than a threshold distance such that the cell can be fabricated by a single-photolithography single-etch process, or ii) the first power-supply-connection via is coupled to first and second substantially parallel conductive lines that extend along directly adjacent tracks.

Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.

Abstract: An electrostatic discharge (ESD) protection scheme for a semiconductor device stacking process is provided, in which an equivalent electrical resistance of a specific path is designed to be less than an equivalent electrical resistance of other paths. Accordingly, when a first active layer and a second active layer in the semiconductor device are stacked, by designing suitable ESD protection cells on such a specific path, electrical charges accumulated on the top layer wafer (or die) select such a specific path over the other paths to be released to the grounded bottom layer wafer (or die), so as to achieve an ESD protection effect. In addition, since such a specific path also serves as a heat dissipation path in a three dimensional integrated circuit (3D IC), an overall heat resistance of the 3D IC may be reduced to improve a heat dissipation effect.

Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.