Abstract: The present technology relates to an intelligent road infrastructure system and, more particularly, to systems and methods for a heterogeneous connected automated vehicle highway (CAVH) network in which the road network has various RSU and TCU/TCC coverages and functionalities. The heterogeneous CAVH network facilitates control and operations for vehicles of various automation level and other road users by implementing various levels of coordinated control among CAVH system entities and providing individual road users with detailed customized information and time-sensitive control instructions, and operations and maintenance services.

Abstract: A method includes forming first and second semiconductor fins and a gate structure over a substrate; forming a first and second source/drain epitaxy structures over the first and second semiconductor fins; forming an interlayer dielectric (ILD) layer over the first and second source/drain epitaxy structures; etching the gate structure and the ILD layer to form a trench; performing a first surface treatment to modify surfaces of a top portion and a bottom portion of the trench to NH-terminated; performing a second surface treatment to modify the surfaces of the top portion of the trench to N-terminated, while leaving the surfaces of the bottom portion of the trench being NH-terminated; and depositing a first dielectric layer in the trench, wherein the first dielectric layer has a higher deposition rate on the surfaces of the bottom portion of the trench than on the surfaces of the bottom portion of the trench.

Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.

Abstract: A near infrared-II region (NIR-II) fluorescent rare earth nanoprobe (RENP) test strip and its preparation method are disclosed. The NIR-II fluorescent RENP test strip includes a sample pad, a conjugation pad, a nitrocellulose (NC) membrane, an absorbent pad and a plastic backing. The sample pad, conjugation pad, NC membrane, absorbent pad are superimposed on the plastic backing successively along a horizontal direction. Detection antibodies labeled RENPs are immobilized on the conjugation pad; capture antibodies set as a test line and quality control antibodies set as a control line are sprayed on the NC membrane. RENPs with NIR-II luminescence are selected as an efficient fluorescent probe, and its excellent optical properties make the prepared test strip possesses excellent detection sensitivity, good accuracy, high stability and favorable repeatability. Meanwhile, preparation process of test strip is also simple and controllable, which is suitable for scale production.

Abstract: This invention provides a system-oriented and fully-controlled connected automated vehicle highway system for various levels of connected and automated vehicles and highways. The system comprises one or more of: 1) a hierarchical traffic control network of Traffic Control Centers (TCC's), local traffic controller units (TCUs), 2) A RSU (Road Side Unit) network (with integrated functionalities of vehicle sensors, I2V communication to deliver control instructions), 3) OBU (On-Board Unit with sensor and V2I communication units) network embedded in connected and automated vehicles, and 4) wireless communication and security system with local and global connectivity. This system provides a safer, more reliable and more cost-effective solution by redistributing vehicle driving tasks to the hierarchical traffic control network and RSU network.

Abstract: The disclosure provides NIR-II imaging probes and methods of using the NIR-II imaging probes for dynamic in vivo tracking of cells, such as stem cells, or other substances. NIR-II imaging probes can include a biocompatible NIR-II dye molecule coupled to an organic, biocompatible protein carrier complex, including a carrier protein coupled to a cell-penetrating peptide.

Abstract: A process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. After forming the edge area, another dielectric fill material is provided in the edge area. In the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.

Abstract: This invention provides a system-oriented and fully-controlled connected automated vehicle highway system for various levels of connected and automated vehicles and highways. The system comprises one or more of: 1) a hierarchical traffic control network of Traffic Control Centers (TCC's), local traffic controller units (TCUs), 2) A RSU (Road Side Unit) network (with integrated functionalities of vehicle sensors, I2V communication to deliver control instructions), 3) OBU (On-Board Unit with sensor and V2I communication units) network embedded in connected and automated vehicles, and 4) wireless communication and security system with local and global connectivity. This system provides a safer, more reliable and more cost-effective solution by redistributing vehicle driving tasks to the hierarchical traffic control network and RSU network.

Abstract: Provided herein are N-acetylgalactosamine (GalNAc)-derived compounds, modified oligonucleotides, and methods of modulating protein function and treating diseases, disorders, and symptoms in a subject.

Abstract: An RRAM structure includes a dielectric layer. A bottom electrode, a resistive switching layer and a top electrode are disposed from bottom to top on the dielectric layer. A spacer is disposed at sidewalls of the bottom electrode, the resistive switching layer and the top electrode. The spacer includes an L-shaped spacer and a sail-shaped spacer. The L-shaped spacer contacts the sidewall of the bottom electrode, the sidewall of the resistive switching layer and the sidewall of the top electrode. The sail-shaped spacer is disposed on the L-shaped spacer. A metal line is disposed on the top electrode and contacts the top electrode and the spacer.

Abstract: In one example method, a server obtains compressed data, where the compressed data includes at least a first part and a second part, and where the compressed data is sorted based on popularity values of parts of the compressed data, and a popularity value of a part of the compressed data is greater than a popularity value of a subsequent part of the compressed data. The server decompresses the first part, and decompresses the second part after decompressing the first part, where a popularity value of the first part is greater than a popularity value of the second part.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes a substrate, semiconductor structures, an isolation layer, an adhesive layer, a metal layer, a metal nitride layer, a semiconductor layer, a profile modifier layer, and a disconnection structure. The semiconductor structures are disposed on the substrate. The isolation layer is disposed between the semiconductor structures. The metal layer is disposed on an adhesive layer. The metal nitride layer is disposed on the metal layer. The semiconductor layer is disposed on the metal nitride layer. The profile modifier layer is disposed on the semiconductor layer. The disconnection structure is disposed and extending from the profile modifier layer to the isolation layer. A first width of the disconnection structure in the profile modifier layer is substantially the same as a second width of the disconnection structure in the isolation layer.

Abstract: In a method for writing data to a solid-state drive, both a byte-level write interface and a page-level write interface are provided. Full-page input/output (I/O) data is written to a flash chip through the page-level interface, and small I/O data is written to a storage class memory (SCM) chip through the byte-level interface.

Abstract: A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first and second epitaxial source/drain structures on opposite sides of the first gate structure, and forming third and fourth source/drain epitaxial structures on opposite sides of the third gate structure; forming first gate spacers, second gate spacers, third gate spacers on opposite sidewalls of the first, second, and third gate structures, respectively; forming a first hard mask over the first, second, and third gate structures; patterning the first hard mask to form a first opening; etching a portion of the second gate structure and a portion of the semiconductor fin through the first opening to form a recess; and forming a dielectric layer in the recess, in which a dielectric constant of the dielectric layer is lower than a dielectric constant of silicon oxide.

Abstract: Methods of forming vias for coupling source/drain regions to backside interconnect structures in semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a conductive feature adjacent a gate structure; a dielectric layer on the conductive feature and the gate structure; a metal via embedded in the dielectric layer; and a liner layer between and in contact with the metal via and the dielectric layer, the liner layer being boron nitride.

Abstract: Transistor gate isolation structures and methods of forming the same are provided. In an embodiment, a device includes: an isolation region; a first gate structure on the isolation region; a second gate structure on the isolation region; and a gate isolation structure between the first gate structure and the second gate structure in a first cross-section, an upper portion of the gate isolation structure having a first concentration of an element, a lower portion of the gate isolation structure having a second concentration of the element, the first concentration different from the second concentration, the lower portion extending continuously along a sidewall of the first gate structure, beneath the upper portion, and along a sidewall of the second gate structure.

Abstract: A method for forming a semiconductor device includes providing a base device having a top dielectric layer, forming a sacrificial layer on the top dielectric layer, and patterning the sacrificial layer to form openings. The method also includes depositing first protective dielectric layer and a low-K dielectric layer in the opening and performing planarization to form a first planarized structure including sacrificial regions and low k regions separated by a first protective layer. Next, top portions of the low-k dielectric layer are replaced with a second protective dielectric layer to form a second planarized structure that includes enclosed dielectric structures separated by sacrificial regions. The method further includes replacing the remaining portions of the sacrificial layer with a target metal interconnect material to form a third planarized structure that includes metal interconnect material disposed between enclosed dielectric structures.

Abstract: Embodiments provide a two-tiered trench isolation structure under the epitaxial regions (e.g., epitaxial source/drain regions) of a nano-FET transistor device, and methods of forming the same. The first tier provides an isolation structure with a low k value. The second tier provides an isolation structure with a higher k value, with material greater density, and greater etch resistivity than the first tier isolation structure.

Abstract: In a method of manufacturing a semiconductor device, a metal gate structure is formed and cut into two pieces of metal gate structures by forming a gate end spaces. A first liner layer is formed in the gate end space, and a sacrificial layer is formed on the first liner layer, and recessed. A second liner layer is formed over the recessed sacrificial layer, an air gap is formed by removing the recessed sacrificial layer; and a third liner layer is formed over the second liner layer.

Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor device structure. In one embodiment, the method includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked, removing edge portions of the second semiconductor layers to form cavities between adjacent first semiconductor layers, selectively forming a passivation layer on sidewalls of the first semiconductor layers, forming a dielectric spacer on sidewalls of the second semiconductor layers and filling in the cavities, wherein the passivation layer is exposed. The method also includes removing the passivation layer, and forming an epitaxial source/drain feature so that the epitaxial source/drain feature is in contact with the first semiconductor layers and the dielectric spacers.