Patents by Inventor Zhen Cheng

Zhen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015131
    Abstract: A method includes the following steps. A transistor including a first gate structure is formed on a first substrate. A first dielectric layer is deposited over the transistor using plasma enhanced atomic layer deposition (PEALD). A multilayer stack is formed on a second substrate. The multilayer stack comprises alternately stacked semiconductor layers and sacrificial layers. A second dielectric layer is deposited over the multilayer stack using a plasma enhanced atomic layer deposition (PEALD). The second dielectric layer is bonded with the first dielectric layer. The sacrificial layers are replaced with a second gate structure.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan Chen HSIEH, Zhen-Cheng WU
  • Patent number: 12172976
    Abstract: Provided are delocalized lipophilic cation (DLC) compounds and methods of using such compounds. Also provided are pharmaceutical compositions that include a DLC compound. Provided methods include methods of killing cells and methods of fluorescently labeling mitochondria by contacting the cells with a DLC compound of the present disclosure. Also provided are methods of imaging cell mitochondria, methods of determining whether a patient has a mitochondria related disease, and methods of treating a patient for a mitochondria related disease. Kits that include compounds of the present disclosure are also provided.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 24, 2024
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Zhen Cheng, Hao Chen
  • Publication number: 20240413220
    Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary method includes depositing a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over a bottom epitaxial source/drain feature formed in a bottom portion of a source/drain trench, etching back the CESL and the ILD layer to expose a top portion of the source/drain trench, performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, where the insulating layer comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench. Method also includes removing the second portion of the insulating layer and forming a top bottom epitaxial source/drain feature on the second portion of the insulating layer and in the source/drain trench.
    Type: Application
    Filed: September 27, 2023
    Publication date: December 12, 2024
    Inventors: Wan Chen Hsieh, Zhen-Cheng Wu, Tai-Jung Kuo
  • Publication number: 20240413230
    Abstract: A semiconductor device includes: a substrate; a fin protruding above the substrate; a gate structure over the fin; source/drain regions over the fin and on opposing sides of the gate structure; channel layers over the fin and between the source/drain regions, where the gate structure wraps around the channel layers; and isolation structures under the source/drain regions, where the isolation structures separate the source/drain regions from the fin, where each of the isolation structures includes a liner layer and a dielectric layer over the liner layer, where the dielectric layer has a plurality of sublayers.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 12, 2024
    Inventors: Mu-Chieh Chang, Shu Ling Liao, Zhen-Cheng Wu, Sung-En Lin, Tze-Liang Lee
  • Publication number: 20240372520
    Abstract: A filter includes a first low-pass filter and a second low-pass filter. The first low-pass filter is located at a first channel, and includes a first resistor array coupled with a complex-signal input terminal. The second low-pass filter is located at a second channel, and includes a second resistor array coupled with the complex-signal input terminal. The complex-signal input terminal is configured to provide complex signals to the first channel and the second channel. The filter further includes a third resistor array and a fourth resistor array. The third resistor array is cross-coupled between the first low-pass filter and the second low-pass filter. The fourth resistor array is coupled between the complex-signal input terminal and the third resistor array. The first resistor array, the second resistor array and the fourth resistor array include variable resistors.
    Type: Application
    Filed: April 17, 2024
    Publication date: November 7, 2024
    Inventor: Zhen Cheng ZHANG
  • Publication number: 20240321572
    Abstract: Provided are semiconductor devices and methods for manufacturing semiconductor devices. A method deposits conformal material to form a conformal liner in the trench and modifies the conformal liner such an upper liner portion is modified more than a lower liner portion. The deposition and modifying steps are repeated while a rate of deposition of the conformal material over a non-modified surface of the conformal liner is faster than a rate of deposition of the conformal material over a modified surface of the conformal liner to form a remaining unfilled gap with a V-shape. The method further includes depositing a conformal material in the remaining unfilled gap.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Fong Lin, Yen-Chun Huang, Zhen-Cheng Wu, Chi On Chui, Chih-Tang Peng, Yu Ying Chen
  • Publication number: 20240323136
    Abstract: A packet transmission method includes: after an output forwarding and processing unit obtains a packet, if the packet belongs to a deterministic flow, storing the packet into a deterministic flow input queue; for each packet in the deterministic flow input queue, determining encapsulation information corresponding to the packet, wherein the encapsulation information at least includes cyclic queue (CQ) queue information; encapsulating the packet based on the encapsulation information, and storing the packet into a deterministic flow output queue; obtaining, by an output interface unit, a packet from the deterministic flow output queue and based on the CQ queue information corresponding to the packet, storing the packet into a CQ queue corresponding to the CQ queue information; determining, by the output interface unit, a target CQ queue corresponding to a current scheduling cycle, and sending a packet in the target CQ queue to an external device within the current scheduling cycle.
    Type: Application
    Filed: December 29, 2021
    Publication date: September 26, 2024
    Applicant: NEW H3C TECHNOLOGIES CO., LTD.
    Inventors: Daorong GUO, Guangliang WEN, Zhen CHENG, Hui LIN
  • Publication number: 20240297038
    Abstract: The present disclosure provides a method. In some embodiments, the method includes forming a first porogen over a dielectric film; depositing a first dielectric monolayer over the first porogen and in contact with the dielectric film; removing the first porogen. In some embodiments, the method includes forming a first porogen over a substrate; forming a first dielectric film over the first porogen; after forming the first dielectric film, performing an UV treatment on the first porogen.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen HO, You-Hua CHOU, Yen-Hao LIAO, Che-Lun CHANG, Zhen-Cheng WU
  • Publication number: 20240250153
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a gate electrode disposed over a semiconductor substrate and a gate cut-fill structure disposed in the gate electrode to separate the gate electrode into two portions. The gate cut-fill structure includes a first liner, a second liner disposed on the first liner, and a dielectric material disposed on the second liner. The dielectric material has a ā€œVā€ shaped cross-section.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 25, 2024
    Inventors: Kun-Yi LIN, Tai-Jung KUO, Yunn-Shiuan LIU, Zhen-Cheng WU, Chi On CHUI
  • Publication number: 20240223655
    Abstract: A data processing system in embodiments of this application includes a storage layer, a virtual bus, and a service layer. The storage layer includes a plurality of storage devices, and the service layer includes a plurality of services. The storage device and/or service may write registration information into the virtual bus after registration, and the registered storage device or service may discover another device or service. Data may move between the storage devices, between the storage devices and the services, and between the services through the virtual bus. In this way, the plurality of devices can discover and communicate with each other when the devices are not directly connected to each other.
    Type: Application
    Filed: March 15, 2024
    Publication date: July 4, 2024
    Inventors: Longwen LAN, Zhuo CHENG, Zhen CHENG, Wen ZHOU, Yi SU
  • Patent number: 12014919
    Abstract: A structure includes a first dielectric film and a second dielectric film. The second dielectric film is formed on and in contact with the first dielectric film, in which a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, You-Hua Chou, Yen-Hao Liao, Che-Lun Chang, Zhen-Cheng Wu
  • Publication number: 20240128375
    Abstract: A method includes forming first and second semiconductor fins and a gate structure over a substrate; forming a first and second source/drain epitaxy structures over the first and second semiconductor fins; forming an interlayer dielectric (ILD) layer over the first and second source/drain epitaxy structures; etching the gate structure and the ILD layer to form a trench; performing a first surface treatment to modify surfaces of a top portion and a bottom portion of the trench to NH-terminated; performing a second surface treatment to modify the surfaces of the top portion of the trench to N-terminated, while leaving the surfaces of the bottom portion of the trench being NH-terminated; and depositing a first dielectric layer in the trench, wherein the first dielectric layer has a higher deposition rate on the surfaces of the bottom portion of the trench than on the surfaces of the bottom portion of the trench.
    Type: Application
    Filed: March 16, 2023
    Publication date: April 18, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Yi CHANG, Yu Ying CHEN, Zhen-Cheng WU, Chi On CHUI
  • Publication number: 20240118198
    Abstract: A near infrared-II region (NIR-II) fluorescent rare earth nanoprobe (RENP) test strip and its preparation method are disclosed. The NIR-II fluorescent RENP test strip includes a sample pad, a conjugation pad, a nitrocellulose (NC) membrane, an absorbent pad and a plastic backing. The sample pad, conjugation pad, NC membrane, absorbent pad are superimposed on the plastic backing successively along a horizontal direction. Detection antibodies labeled RENPs are immobilized on the conjugation pad; capture antibodies set as a test line and quality control antibodies set as a control line are sprayed on the NC membrane. RENPs with NIR-II luminescence are selected as an efficient fluorescent probe, and its excellent optical properties make the prepared test strip possesses excellent detection sensitivity, good accuracy, high stability and favorable repeatability. Meanwhile, preparation process of test strip is also simple and controllable, which is suitable for scale production.
    Type: Application
    Filed: August 27, 2023
    Publication date: April 11, 2024
    Inventors: Zhen Cheng, Zhaorui Song
  • Publication number: 20240120236
    Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 11, 2024
    Inventors: Tai-Jung Kuo, Po-Cheng Shih, Wan Chen Hsieh, Zhen-Cheng Wu, Chia-Hui Lin, Tze-Liang Lee
  • Patent number: 11951187
    Abstract: The disclosure provides NIR-II imaging probes and methods of using the NIR-II imaging probes for dynamic in vivo tracking of cells, such as stem cells, or other substances. NIR-II imaging probes can include a biocompatible NIR-II dye molecule coupled to an organic, biocompatible protein carrier complex, including a carrier protein coupled to a cell-penetrating peptide.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: April 9, 2024
    Assignee: The Board of Trustees of Leland Stanford Junior University
    Inventors: Zhen Cheng, Hao Chen
  • Publication number: 20240113164
    Abstract: A process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. After forming the edge area, another dielectric fill material is provided in the edge area. In the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.
    Type: Application
    Filed: January 9, 2023
    Publication date: April 4, 2024
    Inventors: Heng-Chia Su, Li-Fong Lin, Zhen-Cheng Wu, Chi On Chui
  • Publication number: 20240071850
    Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes a substrate, semiconductor structures, an isolation layer, an adhesive layer, a metal layer, a metal nitride layer, a semiconductor layer, a profile modifier layer, and a disconnection structure. The semiconductor structures are disposed on the substrate. The isolation layer is disposed between the semiconductor structures. The metal layer is disposed on an adhesive layer. The metal nitride layer is disposed on the metal layer. The semiconductor layer is disposed on the metal nitride layer. The profile modifier layer is disposed on the semiconductor layer. The disconnection structure is disposed and extending from the profile modifier layer to the isolation layer. A first width of the disconnection structure in the profile modifier layer is substantially the same as a second width of the disconnection structure in the isolation layer.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: FU-MING HSU, MING-JIE HUANG, ZHEN-CHENG WU, YUNG-CHENG LU
  • Publication number: 20240070120
    Abstract: In one example method, a server obtains compressed data, where the compressed data includes at least a first part and a second part, and where the compressed data is sorted based on popularity values of parts of the compressed data, and a popularity value of a part of the compressed data is greater than a popularity value of a subsequent part of the compressed data. The server decompresses the first part, and decompresses the second part after decompressing the first part, where a popularity value of the first part is greater than a popularity value of the second part.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Inventors: Zhen CHENG, Zengshi HUANG
  • Patent number: D1030649
    Type: Grant
    Filed: February 6, 2024
    Date of Patent: June 11, 2024
    Inventor: Zhen Cheng
  • Patent number: D1038873
    Type: Grant
    Filed: April 3, 2024
    Date of Patent: August 13, 2024
    Inventor: Zhen Cheng