Patents by Inventor Zhen-Cheng Wu

Zhen-Cheng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120236
    Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 11, 2024
    Inventors: Tai-Jung Kuo, Po-Cheng Shih, Wan Chen Hsieh, Zhen-Cheng Wu, Chia-Hui Lin, Tze-Liang Lee
  • Publication number: 20240113164
    Abstract: A process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. After forming the edge area, another dielectric fill material is provided in the edge area. In the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.
    Type: Application
    Filed: January 9, 2023
    Publication date: April 4, 2024
    Inventors: Heng-Chia Su, Li-Fong Lin, Zhen-Cheng Wu, Chi On Chui
  • Publication number: 20240071850
    Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes a substrate, semiconductor structures, an isolation layer, an adhesive layer, a metal layer, a metal nitride layer, a semiconductor layer, a profile modifier layer, and a disconnection structure. The semiconductor structures are disposed on the substrate. The isolation layer is disposed between the semiconductor structures. The metal layer is disposed on an adhesive layer. The metal nitride layer is disposed on the metal layer. The semiconductor layer is disposed on the metal nitride layer. The profile modifier layer is disposed on the semiconductor layer. The disconnection structure is disposed and extending from the profile modifier layer to the isolation layer. A first width of the disconnection structure in the profile modifier layer is substantially the same as a second width of the disconnection structure in the isolation layer.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: FU-MING HSU, MING-JIE HUANG, ZHEN-CHENG WU, YUNG-CHENG LU
  • Publication number: 20230411217
    Abstract: A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first and second epitaxial source/drain structures on opposite sides of the first gate structure, and forming third and fourth source/drain epitaxial structures on opposite sides of the third gate structure; forming first gate spacers, second gate spacers, third gate spacers on opposite sidewalls of the first, second, and third gate structures, respectively; forming a first hard mask over the first, second, and third gate structures; patterning the first hard mask to form a first opening; etching a portion of the second gate structure and a portion of the semiconductor fin through the first opening to form a recess; and forming a dielectric layer in the recess, in which a dielectric constant of the dielectric layer is lower than a dielectric constant of silicon oxide.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsien CHENG, Zhen-Cheng WU
  • Publication number: 20230387012
    Abstract: Methods of forming vias for coupling source/drain regions to backside interconnect structures in semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a conductive feature adjacent a gate structure; a dielectric layer on the conductive feature and the gate structure; a metal via embedded in the dielectric layer; and a liner layer between and in contact with the metal via and the dielectric layer, the liner layer being boron nitride.
    Type: Application
    Filed: August 15, 2022
    Publication date: November 30, 2023
    Inventors: Po-Hsien Cheng, Zhen-Cheng Wu, Tze-Liang Lee, Chi On Chui
  • Publication number: 20230378256
    Abstract: Transistor gate isolation structures and methods of forming the same are provided. In an embodiment, a device includes: an isolation region; a first gate structure on the isolation region; a second gate structure on the isolation region; and a gate isolation structure between the first gate structure and the second gate structure in a first cross-section, an upper portion of the gate isolation structure having a first concentration of an element, a lower portion of the gate isolation structure having a second concentration of the element, the first concentration different from the second concentration, the lower portion extending continuously along a sidewall of the first gate structure, beneath the upper portion, and along a sidewall of the second gate structure.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 23, 2023
    Inventors: Li-Fong Lin, Wen-Kai Lin, Zhen-Cheng Wu, Chi On Chui
  • Publication number: 20230369428
    Abstract: Embodiments provide a two-tiered trench isolation structure under the epitaxial regions (e.g., epitaxial source/drain regions) of a nano-FET transistor device, and methods of forming the same. The first tier provides an isolation structure with a low k value. The second tier provides an isolation structure with a higher k value, with material greater density, and greater etch resistivity than the first tier isolation structure.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 16, 2023
    Inventors: Chih-Hung Sun, Wen-Kai Lin, Che-Hao Chang, Zhen-Cheng Wu, Chi On Chui
  • Publication number: 20230369201
    Abstract: A method for forming a semiconductor device includes providing a base device having a top dielectric layer, forming a sacrificial layer on the top dielectric layer, and patterning the sacrificial layer to form openings. The method also includes depositing first protective dielectric layer and a low-K dielectric layer in the opening and performing planarization to form a first planarized structure including sacrificial regions and low k regions separated by a first protective layer. Next, top portions of the low-k dielectric layer are replaced with a second protective dielectric layer to form a second planarized structure that includes enclosed dielectric structures separated by sacrificial regions. The method further includes replacing the remaining portions of the sacrificial layer with a target metal interconnect material to form a third planarized structure that includes metal interconnect material disposed between enclosed dielectric structures.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Inventors: Po-Hsien Cheng, Zhen-Cheng Wu, TZE-LIANG LEE, Chi On CHUI
  • Publication number: 20230369462
    Abstract: In a method of manufacturing a semiconductor device, a metal gate structure is formed and cut into two pieces of metal gate structures by forming a gate end spaces. A first liner layer is formed in the gate end space, and a sacrificial layer is formed on the first liner layer, and recessed. A second liner layer is formed over the recessed sacrificial layer, an air gap is formed by removing the recessed sacrificial layer; and a third liner layer is formed over the second liner layer.
    Type: Application
    Filed: May 16, 2022
    Publication date: November 16, 2023
    Inventors: Chih-Hung SUN, Po-Hsien CHENG, Zhen-Cheng WU, Chi-On CHUI
  • Publication number: 20230361201
    Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor device structure. In one embodiment, the method includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked, removing edge portions of the second semiconductor layers to form cavities between adjacent first semiconductor layers, selectively forming a passivation layer on sidewalls of the first semiconductor layers, forming a dielectric spacer on sidewalls of the second semiconductor layers and filling in the cavities, wherein the passivation layer is exposed. The method also includes removing the passivation layer, and forming an epitaxial source/drain feature so that the epitaxial source/drain feature is in contact with the first semiconductor layers and the dielectric spacers.
    Type: Application
    Filed: May 7, 2022
    Publication date: November 9, 2023
    Inventors: Wen-Kai LIN, Che-Hao CHANG, Yoh-Rong LIU, Zhen-Cheng WU, Chi On CHUI
  • Publication number: 20230290853
    Abstract: A semiconductor device with doped shallow trench isolation (STI) structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on the fin structure, depositing an oxide liner surrounding the superlattice structure and the fin structure in a first deposition process, forming a dopant source liner on the oxide liner, depositing an oxide fill layer on the dopant source liner in a second deposition process different from the first deposition process, performing a doping process to form a doped oxide liner and a doped oxide fill layer, removing portions of the doped oxide liner, the doped oxide fill layer, and the dopant source liner from sidewalls of the superlattice structure, and forming a gate structure on the fin structure and surrounding the first nanostructured layers.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Jin LI, Che-Hao CHANG, Zhen-Cheng WU, Chi On CHUI
  • Publication number: 20230268384
    Abstract: A semiconductor structure according to the present disclosure includes a base fin over a substrate, a stack of nanostructures disposed directly over the base fin, a gate structure wrapping around each of the stack of nanostructures, an isolation feature disposed over the substrate and adjacent the base fin, and a dielectric fin disposed directly on the isolation feature. The dielectric includes in a bottom portion, a middle layer over the bottom portion and a top layer over the middle layer. The bottom portion includes an outer layer and an inner layer spaced apart from the gate structure and the isolation feature by the outer layer. The middle layer is in direct contact with top surfaces of the inner layer and the outer layer. The dielectric constant of the top layer of the dielectric fin is greater than the dielectric constant of the middle layer.
    Type: Application
    Filed: May 23, 2022
    Publication date: August 24, 2023
    Inventors: Tai-Jung Kuo, Zhen-Cheng Wu, Chung-Ting Ko, Sung-En Lin, Chi On Chui
  • Publication number: 20230154984
    Abstract: In an embodiment, a device includes: first source/drain regions; a first insulating fin between the first source/drain regions, the first insulating fin including a first lower insulating layer and a first upper insulating layer; second source/drain regions; and a second insulating fin between the second source/drain regions, the second insulating fin including a second lower insulating layer and a second upper insulating layer, the first lower insulating layer and the second lower insulating layer including the same dielectric material, the first upper insulating layer and the second upper insulating layer including different dielectric materials.
    Type: Application
    Filed: May 12, 2022
    Publication date: May 18, 2023
    Inventors: Chung-Ting Ko, Tai-Jung Kuo, Sung-En Lin, Zhen-Cheng Wu, Chi On Chui
  • Publication number: 20230040843
    Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure includes a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed at a bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer over the seed layer at the bottom of the opening; and selectively growing a source/drain material on opposing sidewalls of the second semiconductor material exposed by the opening.
    Type: Application
    Filed: April 8, 2022
    Publication date: February 9, 2023
    Inventors: Chun-Ming Lung, Che-Hao Chang, Zhen-Cheng Wu, Chi On Chui
  • Publication number: 20210202241
    Abstract: A structure includes a first dielectric film and a second dielectric film. The second dielectric film is formed on and in contact with the first dielectric film, in which a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore.
    Type: Application
    Filed: March 11, 2021
    Publication date: July 1, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen HO, You-Hua CHOU, Yen-Hao LIAO, Che-Lun CHANG, Zhen-Cheng WU
  • Patent number: 10950426
    Abstract: A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, You-Hua Chou, Yen-Hao Liao, Che-Lun Chang, Zhen-Cheng Wu
  • Publication number: 20200058495
    Abstract: A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen HO, You-Hua CHOU, Yen-Hao LIAO, Che-Lun CHANG, Zhen-Cheng WU
  • Patent number: 10361152
    Abstract: A semiconductor structure comprises a first conductive material-containing layer. The first conductive material-containing layer comprises a dielectric material, at least two conductive structures in the dielectric material, and an air-gap region in the dielectric material between the at least two conductive structures. The semiconductor structure also comprises a capping layer over the at least two conductive structures and the air-gap region. The semiconductor structure further comprises a second conductive material-containing layer over the capping layer. The second conductive material-containing layer comprises a via plug electrically connected to one of the at least two conductive structures. The via plug is separated from the air-gap region by at least a first predetermined distance. The semiconductor structure additionally comprises a conductive pad over the second conductive material-containing layer. The conductive pad is offset from the air-gap region by at least a second predetermined distance.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 9178086
    Abstract: A method for fabricating back-contact type solar cells is provided. The method comprises forming a plurality of n-type doped zones, a plurality of p-type doped zones, and a back anti-reflection layer on a back surface of a semiconductor substrate. The lead-containing conductive paste may pass through the back anti-reflection layer and connect to the n-type doped zones and the p-type doped zones thereby being regarded as n-type electrodes and p-type electrodes.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: November 3, 2015
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yen-Cheng Hu, Jen-Chieh Chen, Zhen-Cheng Wu
  • Patent number: 9136226
    Abstract: An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhen-Cheng Wu, Yung-Cheng Lu, Chung-Chi Ko