Abstract: A glucose-responsive insulin complex, a preparation method and a use thereof. The glucose-responsive insulin complex includes phenylboronic acid-based polylysine and insulin with a diol structure, wherein interaction forces include: a dynamic electrostatic attraction, and a diol-PBA complexation force between the phenylboronic acid-based polylysine and the insulin with a diol structure.

Abstract: Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.

Abstract: Methods, systems, and devices for techniques for a fragment cursor are described. A memory system may receive one or more write commands, each write command corresponding to a data fragment. The memory device may store the data fragments to a cursor (e.g., a fragment cursor) in a cache upon receiving the write commands, the cursor configured to store data fragments with a size less than a fragment size threshold (e.g., a page). The memory system may detect a memory management operation (e.g., power down, cache synchronization, data relocation, etc.) and write the cached data fragments to a block of memory cells of a memory device using the cursor. In some examples, the cursor may have a different associated mapping unit than other cursors of the memory system.

Abstract: The present application discloses a fabrication method for an integrated structure of transistors with different operating voltages. A high-voltage transistor area and a low-voltage transistor area are protected by a retained hard mask layer before a medium-voltage gate oxide layer is grown, so as to avoid additional growth of gate oxide layers above active areas of the high-voltage transistor area and the low-voltage transistor area, thereby avoiding the deterioration of a step height of the low-voltage transistor area due to the subsequent use of a large amount of acid to remove the gate oxide layer additionally grown above the active area of the low-voltage transistor area, and preventing the electrical property and the reliability of a low-voltage device from being subsequently influenced while avoiding the influence of the etching with the large amount of acid on the thickness of a high-voltage gate oxide layer which has already been grown.

Abstract: A retinoic acid modified lysosome targeting chimera (LYTAC) molecule, a preparation method and applications thereof are provided. A structural formula of the retinoic acid modified LYTAC molecule is in which, n represents a molecular weight of polyethylene glycol (PEG), n is in a range of 60 to 5000, R is one of an antibody, a polypeptide and a micromolecule compound targeting a targeted protein. The retinoic acid modified LYTAC molecule can be applied to targeted protein degradation and preparation of tumor cell activity inhibitors. Retinoic acid has high biosafety, is easy to obtain and modify, and has a broad application prospect.

Abstract: This application discloses a CIS pixel readout circuit structure. An SG and an SF adopt different transverse thicknesses of spacers. The spacer of the SG adopts a smaller transverse thickness to reduce the parasitic resistance. The spacer of the SF adopts a larger transverse thickness to reduce the GIDL current. In the CIS pixel readout circuit structure according to this application, drain metal plugs are formed on outer sides of both left and right ends of an SF gate structure. The SF and the SG form a T-shaped combined compact structure to achieve equivalent parallel connection of two SF, thus effectively reducing the parasitic resistance of the share active area between the SG and the SF, and simultaneously saving the space area. This application further discloses a method for fabricating a CIS pixel readout circuit structure.

Abstract: A multiplication unit includes first, second, third and fourth receiving terminals, arithmetic units and multiplexers. In complex number mode, the first and second receiving terminals receive a real part value and an imaginary part value of a first complex number, respectively, whereas the third and fourth receiving terminals receive a real part value and an imaginary part value of a second complex number, respectively. In modulus mode, the first and third receiving terminals receive first and second integers, respectively. The multiplexers gate the arithmetic units to perform a complex number multiplication operation according to the first and second complex numbers to generate a third complex number in complex number mode and perform a modulus multiplication operation according to the first and second integers and a predetermined modulus to generate a third integer in modulus mode.

Abstract: Methods, systems, and devices for a sorted change log for physical page table compression are described. A mapping between a logical address and a physical address may be stored in a change log buffer. The mapping may be stored at a location of the change log buffer based on the logical address of the mapping relative to logical addresses of other mappings stored in the change log buffer. Based on storing mappings in the change log buffer based on logical addresses of the mappings, a set of mappings in the change log may include a set of sequentially-indexed logical addresses. A compressed entry for a logical-to-physical table may be generated based on the set of mappings.

Abstract: Methods, systems, and devices for memory management procedures for write boost mode are described. A memory system may receive a command to write data. The memory system may write the data to a first location of the memory system using a first mode for storing one bit per memory cell based on receiving the command. The memory system may select a first portion of the data to rewrite to the memory system using a second mode for storing two or more bits per memory cell based on one or more parameters satisfying one or more thresholds. The memory system may write the first portion of the data to a second location of the memory system using the second mode based on selecting the first portion of the data. The memory system may maintain a second portion of the data at the first location of the memory system.

Abstract: This application discloses a CIS pixel readout structure. An SF and an SG adopt an asymmetric spacer structure, so that the pitch from a lower end of a source metal plug of the SG to SG gate poly can be reduced while keeping the pitch from a lower end of a drain metal plug of the SF to SF gate poly unchanged, thus reducing the pitch from a drain connecting point of the SF to a source connecting point of the SG. Since a source of the SG is not connected with working voltage and it is not influenced by leakage, not only can GIDL current be maintained, but also parasitic resistance can be reduced. Without changing its effective size, it can reduce the parasitic resistance effect while reducing the area of a combined structure of the SF and the SG.

Abstract: This application discloses a CIS pixel readout circuit structure. An SG and an SF adopt different transverse thicknesses of spacers. The spacer of the SG adopts a smaller transverse thickness to reduce the parasitic resistance. The spacer of the SF adopts a larger transverse thickness to reduce the GIDL current. In the CIS pixel readout circuit structure according to this application, drain metal plugs are formed on outer sides of both left and right ends of an SF gate structure. The SF and the SG form a T-shaped combined compact structure to achieve equivalent parallel connection of two SF, thus effectively reducing the parasitic resistance of the share active area between the SG and the SF, and simultaneously saving the space area. This application further discloses a method for fabricating a CIS pixel readout circuit structure.

Abstract: Methods, systems, and devices for memory management procedures for write boost mode are described. A memory system may receive a command to write data. The memory system may write the data to a first location of the memory system using a first mode for storing one bit per memory cell based on receiving the command. The memory system may select a first portion of the data to rewrite to the memory system using a second mode for storing two or more bits per memory cell based on one or more parameters satisfying one or more thresholds. The memory system may write the first portion of the data to a second location of the memory system using the second mode based on selecting the first portion of the data. The memory system may maintain a second portion of the data at the first location of the memory system.

Abstract: Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.

Abstract: Disclosed herein is a particle containing an inner liposomal vesicle (ILV) encapsulating a therapeutic agent; an outer liposomal vesicle (OLV) encapsulating the ILV; a membrane fusion-promoting agent; and a pH-altering agent. Also disclosed are methods of delivering a therapeutic agent to a subject comprising: a) providing a herein disclosed particle b) triggering ILV and OLV fusion; and c) releasing the therapeutic agent outside of the OLV. Also disclosed are methods for treating a disease in a subject in need thereof comprising: administering to a subject a herein disclosed particle. Also disclosed are methods to release insulin to an environment comprising increased glucose levels, the method comprising exposing to the environment a herein disclosed particle.

Abstract: Disclosed are therapeutic agent delivery vehicle comprising a modified platelet comprising a therapeutic agent cargo and a targeting moiety and methods for treating cancer comprising administering the same to a subject.

Abstract: Disclosed are compositions and methods for microneedle patches comprising copolymer designed for glucose triggered insulin delivery. In one aspect, disclosed herein are microneedle patches comprising insulin loaded copolymers; wherein the insulin dissociates from the microneedle in an hyperglycemic environment; wherein the copolymer comprises poly(N-vinylpyrrolidone-co-2-N(dimethylamino)ethyl acrylate-co-3-(acrylamido)phenylboronic acid and methods of their use.

Abstract: Methods, systems, and devices for logical-to-physical (L2P) mapping compression techniques are described. A memory system may use an L2P mapping to map logical addresses to physical addresses of the memory system. The L2P mapping may be a hierarchical L2P mapping divided into multiple levels or subsets that are used to identify a physical address corresponding to a logical address. The memory system may write data to a set of physical addresses that are consecutively indexed and may set a flag in an entry of a second-level of the L2P mapping (e.g., of a three-level L2P mapping) to indicate that the entry is associated with a starting physical address of the consecutively indexed physical addresses. The memory system may subsequently read the data starting at the starting physical address based on the flag (e.g., bypassing reading an entry of a lowest-level of the L2P mapping to determine the physical address).

Abstract: A bioorthogonal catalytic patch integrates TiO2 nanosheets populated with metallic nanoparticles into polyvinyl alcohol-based microneedles arranged in an array. This bioorthogonal patch-based device is robust, removable and can effectively mediate the conversion of caged substrates into their active states once placed at the site of application. The capacity of the patch in executing bioorthogonal catalysis in high-level living systems was demonstrated by localized dealkylation of a caged doxorubicin prodrug at the melanoma tumor site and restoration of its pharmacological properties for cancer therapy. This in situ applied patch facilitated to enhance the local treatment efficacy and eliminate off-targeted prodrug activation or dose-dependent side effect towards healthy organs or tissues located away from the application site.

Abstract: The present application discloses a super flash, wherein a device cell includes a first gate trench at the top of a source region, a first spacer structure is formed on a side surface of the first gate trench in a self-aligned manner, and the first spacer structure is formed by means of self-aligned etch of a stack layer of a first tunneling dielectric layer, a floating gate, and a second oxide layer. The material of the floating gate comprises a TiN layer. A second spacer structure is formed on a second side surface of the first spacer structure in a self-aligned manner, and the second spacer structure is formed by means of self-aligned etch of a stack layer of a third silicon nitride layer, a fourth oxide layer, and a fifth silicon nitride layer. The present application further discloses a method for manufacturing a super flash.

Abstract: A privacy calculation unit includes a first calculation subunit, a storage subunit, and a communication subunit. The first calculation subunit includes circuitry to calculate first domain conversion ciphertexts sequentially. The storage subunit is configured to store the calculated first domain conversion ciphertexts received from the first calculation subunit. The first domain conversion ciphertext is an intermediate ciphertext when first to-be-converted data is converted from a first privacy-preserving computation domain to a second privacy-preserving computation domain.