Abstract: A power converter includes a power stage circuit, a ramp generator circuit, and a control circuit. The power stage circuit generates an output signal according to an input signal and a control signal. The ramp generator circuit generates a ramp signal according to the control signal, the input signal, and the output signal. The control circuit generates the control signal according to the output signal, a reference signal, and the ramp signal.

Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.

Abstract: Provided are compounds useful for treating of cancer and methods for treating of cancer, comprising administering to a subject in need thereof a compound described therein.

Abstract: A stability control method for a virtual synchronous generator (VSG) in a strong grid based on an inductance-current differential feedback is provided. A grid-connected topological structure of a VSG using the control method includes a direct-current (DC)-side voltage source, a three-phase inverter, a three-phase grid impedance and a three-phase grid. By controlling the VSG and controlling the inductance-current differential feedback, the method suppresses the oscillation of the output power from the VSG in the strong grid and implements the stable operation of an inner-loop-free VSG in the strong grid, without adding the physical inductance, increasing the cost of the filter and additionally providing a grid-side current sensor.

Abstract: The present application provides an instruction encoding-based data processing method and apparatus, and a device. N-path error correction encoding is performed on an instruction in information to be processed to obtain N encoded instructions, the encoded instructions and encoded meta channel programs obtained by the error correction encoding are used to perform redundant processing on data to be processed to obtain N pieces of response data, and then error correction decoding is performed on the N pieces of response data to obtain processing result information of the information to be processed. Because the N encoded instructions are heterogeneous and the encoded meta channel programs used in the N-path processing are heterogeneous, the randomness of the processing process can be improved, generalized disturbance in the data processing process can be corrected in combination with the error correction encoding and decoding methods, and thus the security of data processing is improved.

Abstract: A heparin skeleton synthase originates from Neisseria animaloris, with an amino acid sequence as shown in SEQ ID NO.2 and a nucleotide sequence of the coding gene as shown in SEQ ID NO.1. Its recombinant expression level is 6.8 times that of the existing heparin skeleton synthase KfiA from Escherichia coli K5, and total enzyme activity per fermentation liquor is 5.22 times that of the heparin skeleton synthase KfiA. The heparin skeleton synthase mutants obtained through site-directed mutagenesis of the sites No. 16, No. 25, No. 30, No. 111, No. 165, and No. 172 in the amino acid sequence of the said heparin skeleton synthase all have high expression levels.

Abstract: Isolated power supply control circuits, isolated power supply and control method thereof are disclosed, the control circuit for controlling an isolated power supply includes a secondary-side control signal generator and a primary-side control signal generator. The secondary-side control signal generator produces a secondary-side transistor switch control signal containing information about a turn-off instant of a secondary-side synchronous rectification transistor, which serves as a second turn-on instant. The primary-side control signal generator derives, from a feedback signal, a supposed turn-on instant for a primary-side transistor switch, which serves as a first turn-on instant. The primary side turn-on signal generator further derives a turn-on instant for the primary-side transistor switch from the second or first turn-on instant whichever is later and responsively generates a primary-side transistor switch control signal.

Abstract: Herbal composition having an effect of reducing uric acid, which is made from the following herbal materials in specified portions by weight: 4-30 portions of Glabrous greenbrier rhizome, 2-15 portions of Chicory, 2-15 portions of Herba Plantaginis, 2-20 portions of Coix seed, and 2-10 portions of Kudzuvine Root. The composition may be used in combination with modern Western medicines to achieve optimal effects.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. The semiconductor device includes a first landing pad on a first gate layer of a first stair step. The first gate layer is a top gate layer of the first stair step. The semiconductor device further includes a first sidewall isolation structure on a riser sidewall of a second gate layer of a second stair step. The second gate layer is a top gate layer of the second stair step and is stacked on the first gate layer in the memory stack. The first sidewall isolation structure isolates the second gate layer from the first landing pad.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for jointly training an image embedding model and a text embedding model. In one aspect, a method comprises: processing data from a historical query log of a search system to generate a candidate set of training examples, wherein each training example comprises: (i) a search query comprising a sequence of one or more words, (ii) an image, and (iii) selection data characterizing how often users selected the image in response to the image being identified by a search result for the search query; selecting a plurality of training examples from the candidate set of training examples; and using the training data to jointly train the image embedding model and the text embedding model.

Abstract: Disclosed herein are batteries and methods of making batteries. The batteries disclosed herein generally comprise a cathode, an electrolyte capable of conducting protons and/or hydronium ions, and an anode comprising a material capable of absorbing protons and/or hydronium ions, wherein (i) the cathode is in contact with a cathode substance, or (ii) the electrolyte comprises a reduced cathode substance, or (iii) the cathode is in contact with a cathode substance and the electrolyte comprises a reduced cathode substance, and wherein the cathode substance is an oxide of one or more metals or an oxide of a halide.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. Further, the semiconductor device includes a landing stack formed on the stair steps in the staircase region. The landing stack includes an upper layer that is etch selective to a contact isolation layer that covers the staircase region. Then, the semiconductor device includes a first contact structure on a first stair step of the stair steps. The first contact structure extends through a first contact hole in the contact isolation layer and the landing stack. The first contact structure is connected with a first gate layer (e.g., a top gate layer) of the first stair step.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers, a landing structure and a contact structure. The gate layers and the insulating layers are stacked alternatingly, and form stair steps in a staircase region. The landing structure is disposed on a first gate layer of a first stair step of the stair steps in the staircase region. The landing structure includes an upper structure and an isolation stack between the upper structure and the first gate layer. The upper structure is etch-selective to a contact isolation layer that covers the staircase region. The contact structure extends through the contact isolation layer and the landing structure and is connected with the first gate layer of the first stair step.

Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.

Abstract: The present invention provides a method and system for diagnosing a central nervous system disease, and a composition, and a kit. The diagnosing system comprises: a first detection module, used for detecting a central nervous system-derived marker in a biological body fluid of a subject; a second detection module, used for detecting a central nervous system disease-related marker in the biological body fluid of the subject; and a diagnosis module, diagnosing, on the basis of central nervous system-derived marker and central nervous system disease-related marker detection results respectively obtained by the first detection module and the second detection module, whether the subject suffers from a central nervous system disease.

Abstract: The present disclosure provides a touch screen, a manufacturing method thereof, and a touch display device. The touch screen includes: a substrate; a touch layer and a bonding layer that are on a side of the substrate, the bonding layer being connected to the touch layer by a metal wire; a flexible circuit board connected to the bonding layer; a polarizer on a side of the touch layer away from the substrate and provided with a notch exposing the bonding layer and at least a portion of the metal wire; an insulating light-shielding strip covering the portion of the metal wire exposed by the notch and extending to a side of the polarizer close to the substrate; and a cover plate on a side of the polarizer away from the substrate and including a transparent window area and a shielding area around the transparent window area.

Abstract: A method of fabricating a three-dimensional memory includes forming a laminated structure including stacked dummy gate layers and interlayer insulation layers on one side of a substrate. The respective adjacent dummy gate layers and interlayer insulation layers form staircase stairs. At least a part of the interlayer insulation layer of each of the staircase stairs is exposed. The method also includes forming a buffer layer covering the staircase stairs. The method further includes removing a part of the buffer layer covering the sidewalls of the staircase stairs to form spacing grooves. The method further includes forming a dielectric layer that fills the spacing grooves and covers the staircase stairs. The method further includes forming a contact hole penetrating through the dielectric layer and the buffer layer and extending to the dummy gate layer farthest from the substrate.

Abstract: A method to treat the magnesium surface to manufacture the metallic assembly with the polymer and magnesium to have excellent bonding strength is disclosed. As a method to treat the magnesium surface for the bonded coupling of the mixture of the polymer and magnesium, this is a method including, (a) an etching step, wherein the magnesium surface is treated with an acidic solution; (b) a first surface treatment step, wherein the magnesium surface is treated with ultrasonic waves; (c) a second surface treatment step, wherein the magnesium surface is treated with an acidic solution; (d) a first silane coupling processing step, wherein the magnesium surface is treated with ultrasonic waves; (e) a surface activation treatment step, wherein the magnesium surface is treated with acidic solution; and (f) a second silane coupling processing step, wherein the magnesium surface is treated with ultrasonic waves.

Abstract: A pile-side lateral static load device includes a jack system, a liftable jack cart, a loading jack fixing system, and a loading system. The jack system includes a jack body. The jack system is installed on the liftable jack cart through the loading jack fixing system. The loading system is installed on the loading jack fixing system, and the loading system includes counter-pressure loading systems and counter-tension loading systems. The pile-side lateral static load device has a simple structure, is convenient to install and operate, and can complete lateral loading and in-situ tests under different pile diameters, different tonnages and different precisions, so as to facilitate a simulation test of in-situ lateral loading of a pile.