Abstract: An integrated circuit includes first to second transistors and a resistive device. The first transistor is coupled between a pad and a first voltage terminal that provides a first supply voltage. The second transistor is coupled in parallel with the first transistor. A breakdown voltage of the first transistor is different from a trigger voltage of the second transistor. The resistive device is coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, and operates with the second supply voltage in an electrostatic discharge (ESD) event when the first and second transistors discharge a ESD current between the pad and the first voltage terminal.

Abstract: In a method of operating a circuit, at a beginning of a first edge of a driving signal, a first transistor is turned ON to pull, at a first changing rate, a voltage of the driving signal on the first edge from a first voltage toward a second voltage. Then, in response to the voltage of the driving signal on the first edge reaching a threshold voltage between the first voltage and the second voltage, the first transistor is turned OFF and an output circuit is caused to start a second edge of an output signal in response to the first edge of the driving signal. The second edge has a slew rate corresponding to a second changing rate of the voltage of the driving signal on the first edge from the threshold voltage toward the second voltage. The second changing rate is controlled by a passive circuit and is smaller than the first changing rate.

Abstract: Systems and methods for wireless communications are disclosed herein. A base station sends, to a wireless communication device, a first number of Transmitted Precoding Matrix Indicators (TPMI) codewords corresponding to a second number of codebook-based uplink transmissions of the wireless communication device. The first number being greater or equal to 1. The second number being greater or equal to 1. The first number of TPMI codewords correspond to an uplink transmission set. The uplink transmission set including the second number of the uplink transmissions. The base station receives, from the wireless communication device, the codebook-based uplink transmissions transmitted based on the TPMI codewords.

Abstract: An information transmission method and apparatus, and a storage medium are provided. The information transmission method includes: determining, according to information, a time unit in which an aperiodic measurement reference signal resource is located; and transmitting or receiving the aperiodic measurement reference signal resource in the time unit in which the aperiodic measurement reference signal resource is located, wherein the information comprises: a minimum time interval between a Physical Downlink Control Channel (PDCCH) scheduling the aperiodic measurement reference signal resource and the aperiodic measurement reference signal resource, slot structure information, a sub-carrier spacing, and a set of time-domain symbols comprising all time-domain symbols occupied by measurement reference signal resources in a first measurement reference signal resource set in which the aperiodic measurement reference signal resource is located, wherein the time unit is a slot.

Abstract: In one example, a semiconductor device includes a conductive layer, composite structures, conductive posts and first pads. The composite structures may be located on the conductive layer and stacked in a direction perpendicular to the plane in which the conductive layer is located. The composite structure may include a chip, an insulating layer surrounding around the chip, and at least one second pad electrically connected with the chip. The second pad is located on the insulating layer. The second pads of the composite structures are at different locations in the first direction. The first direction is perpendicular to the thickness direction of the composite structures. The conductive posts are located in the insulating layer of the composite structures and each conductive post is connected with one of the second pads and one of the first pads.

Abstract: Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.

Abstract: Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.

Abstract: Implementations of the present disclosure include a semiconductor structure comprising a stack structure comprising a first stack layer and a second stack layer stacked together, wherein a first region and a second region surrounding the first region are disposed in the stack structure, and a first surface of the first region and a first surface of the second region are coplanar; and a filling structure located on a second surface of the second region, wherein the second surface and the first surface of the second region are respectively two surfaces of the second region disposed oppositely in a first direction that is parallel to a stack layer extending direction of the stack structure.

Abstract: Examples of the present disclosure propose a semiconductor structure and a fabrication method thereof, a memory device, and a memory system. The semiconductor structure includes at least one deck structure. The fabrication method of the deck structure includes: providing a first stack structure in which a peripheral circuit is disposed; forming a first contact and a second contact at least penetrating through the first stack structure; providing a second stack structure in which a memory cell array is disposed; forming a third contact and a fourth contact penetrating through the second stack structure; stacking and bonding the first stack structure and the second stack structure along a first direction to form the deck structure, wherein the first contact is connected with the third contact by bonding to form a first interconnection structure, and the second contact is connected with the fourth contact by bonding to form a second interconnection structure.

Abstract: The present disclosure discloses a memory, a fabrication method thereof, and a memory system. According to an example, the memory includes a substrate, a device layer, a padding layer and a buffering protection layer. The device layer is disposed on the substrate, the padding layer is disposed at a first side of the device layer, the buffering protection layer is disposed on a second side of the device layer and a side of the padding layer away from the substrate. The padding layer is disposed to be adjacent to the device layer in a direction parallel to the substrate.

Abstract: An example computing device includes a printed circuit board comprising: a first layer including one or more ground signal paths; a second layer including one or more ground signal paths; a third layer disposed between the first layer and the second layer; a radar antenna portion comprising a first radar antenna and electrically connected to a distal connector of the printed circuit board; a radar clock signal line configured to convey a radar clock signal between the radar antenna portion and the distal connector; and a first ground guard trace electrically coupled to the one or more ground signal paths and positioned adjacent to a first side of the radar clock signal line and parallel to a length of the radar clock signal line.

Abstract: Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.

Abstract: A boltless fastener assembly for a heavy haul railway with an axle load of 35-40 tons includes a pre-embedded steel holder, an e-clip, an insulated gauge block and a rubber pad. A clamping leg-heel end of the e-clip is provided with an L-shaped retaining end. The pre-embedded steel holder is improved to adapt to the e-clip, and an opening is formed at a portion of the pre-embedded steel holder close to the clamping leg-heel end of the e-clip, so that the e-clip can be installed normally. During normal installation, the L-shaped retaining end of the e-clip does not contact the pre-embedded steel holder. When the rail undergoes large torsional deformation, the L-shaped retaining end on one side of a rail moves upward to contact an upper edge of the opening of the pre-embedded steel holder or engages with a second heel end.

Abstract: A boltless fastener assembly for a heavy haul railway with an axle load of 35-40 tons includes a pre-embedded steel holder, an e-clip, an insulated gauge block and a rubber pad. A clamping leg-heel end of the e-clip is provided with an L-shaped retaining end. The pre-embedded steel holder is improved to adapt to the e-clip, and an opening is formed at a portion of the pre-embedded steel holder close to the clamping leg-heel end of the e-clip, so that the e-clip can be installed normally. During normal installation, the L-shaped retaining end of the e-clip does not contact the pre-embedded steel holder. When the rail undergoes large torsional deformation, the L-shaped retaining end on one side of a rail moves upward to contact an upper edge of the opening of the pre-embedded steel holder or engages with a second heel end.

Abstract: A medical hydrogel is formed by in-situ crosslinking an aldehyde-terminated multi-arm star polyethylene glycol and a polyamino compound. The aldehyde group and the multi-arm star polyethylene glycol are linked by a chemical bond such as an ether bond, an amide bond, an ester bond, a urethane bond, an imine bond, or a urea bond. The molar ratio of the amino in the polyamino compound to the aldehyde group in the aldehyde-terminated multi-arm star polyethylene glycol is 0.4-4.4:1. The polyamino compound is polylysine or a mixture of polylysine and polyethylenimine in a molar ratio of 2-30:3.

Abstract: A medical hydrogel is formed by in-situ crosslinking an aldehyde-terminated multi-arm star polyethylene glycol and a polyamino compound. The aldehyde group and the multi-arm star polyethylene glycol are linked by a chemical bond such as an ether bond, an amide bond, a urethane bond, an imine bond, or a urea bond. The aldehyde group at the end of the multi-arm polyethylene glycol reacts with the amino group in the polyamino compound to produce Schiff base for crosslinking so that the medical injectable gel is formed. The prepared gel has a short gelling time, a desired gel burst strength, and a good stability in an aqueous solution.

Abstract: Hot-plug actions are enabled in an M-host, N-card system architecture. An arbiter receives status signals from the N hot-pluggable cards, and transfers the status signals to at least some of the M host devices. In response to the status signals indicating a hot-plug action, the arbiter receives at least one host command. The arbiter transfers the host command to one or more of the N hot-pluggable cards according to an arbiter algorithm.

Abstract: Hot-plug actions are enabled in an M-host, N-card system architecture. An arbiter receives status signals from the N hot-pluggable cards, and transfers the status signals to at least some of the M host devices. In response to the status signals indicating a hot-plug action, the arbiter receives at least one host command. The arbiter transfers the host command to one or more of the N hot-pluggable cards according to an arbiter algorithm.

Abstract: The present invention is directed to antibodies which bind human gp39, are antagonistic of the CD40/CD40L interaction, but are non-agonistic of T-cell activation. The present invention is further directed to the use of these antibodies as therapeutic agents. These antibodies are especially useful for treatment of autoimmune diseases; and an immunosuppressant during transplantation of heterologous cells, tissues or organs, cell therapy, and gene therapy.

Abstract: Novel human monoclonal antibodies, and their corresponding nucleic acid sequences having high affinity for the human RSV-F protein are provided.