Abstract: The present application provides a data access method based on device passthrough of a virtual machine, a device and a system. The method includes the following steps.

Abstract: Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created.

Abstract: Layout simulation and verification of a semiconductor chip can require extensive design rule checking (DRC) and design rules for manufacturing (DRM) analysis of the design in order to ensure proper operation. DRC and DRM can be expensive in terms of computational time and resource usage. To mitigate some of the cost, a virtual layer can be constructed for a cell instance identified in the semiconductor design. Shapes including rectangles and polygons can be determined which traverse the cell instance and are from other hierarchical layers of the design. The shapes can be combined to generate a virtual layer used for simulation, validation, DRC, DRM, etc. The virtual layer can be augmented with traversing shape information from other instances of the cell. The rectangles, polygons, and complex polygons can be combined to simplify the virtual layer. Multiple virtual layers can be generated for the simulation and validation processes.

Abstract: Techniques for a mild hybrid vehicle utilize a control system for detecting a deceleration fuel shutoff (DFSO) event where fueling to an engine is disabled and in response to detecting the DFSO event: determining a desired pumping loss for the engine based on a parameter of a battery system, the desired pumping loss corresponding to a desired amount of electrical energy that a motor generator unit (MGU) of a belt-driven starter generator (BSG) system will generate to charge the battery system; commanding a throttle valve of the engine to an initial position determined based on the desired engine pumping loss and a speed of the engine; estimating an actual pumping loss of the engine based on an estimated airflow into the engine; and adjusting the position of the throttle valve based on a difference between the desired and actual engine pumping losses.

Abstract: Provided are an inter-eNodeB communication method and device, wherein the method includes that: an inter-eNodeB interface transmission condition is detected, a cooperation mode of inter-eNodeB communication is determined according to the inter-eNodeB interface transmission condition, and the inter-eNodeB communication is performed according to the cooperation mode. The present disclosure solves the problem of inter-eNodeB cooperation in different inter-eNodeB interface conditions in the related art, thus improving the effect of the inter-eNodeB cooperation.

Abstract: The present document discloses a method, apparatus and system for indicating downlink resources of a coordinated multi-point network in an LTE system. The method includes: determining a control station/cell and a service station/cell of a User Equipment (UE); and indicating through signaling that a Physical Downlink Shared Channel (PDSCH) of the UE occupies radio resources of the service station/cell in a control region, whereby a start position of the PDSCH allocated for the UE by the service station/cell is the first symbol of a subframe, and when a resource mapping in the control region is performed, the PDSCH does not occupy Resource Elements (REs) occupied by a Cell Reference Signal (CRS), a Physical Control Format Indicator Channel (PCFICH), a Physical Hybrid-ARQ Indicator Channel (PHICH) of a station/cell where the PDSCH is located, and a Physical Downlink Control Channel PDCCH of the UE.

Abstract: Simulation and verification are critical to analyzing a semiconductor design using design rule checking (DRC) to verify design rules for manufacturing (DRM). The efficient use of computational resources including runtimes and resource requirements is a key component of the analysis. A virtual hierarchical layer (VHL) with shapes is generated for the design analysis of a design, including cells and hierarchical design levels. A cell and multiple instances of the cell are identified in the design. A VHL based on polygons overlapping the cell is generated in response to an algorithmic operation. The VHL shapes are propagated to subsequent algorithmic operations. The algorithmic operations update the VHL shapes. Shapes are filtered out of the VHL shapes as part of the updating. The VHL shapes are propagated through a chain of operations.

Abstract: The present document discloses a method, apparatus and system for indicating downlink resources of a coordinated multi-point network in an LTE system. The method includes: determining a control station/cell and a service station/cell of a User Equipment (UE); and indicating through signaling that a Physical Downlink Shared Channel (PDSCH) of the UE occupies radio resources of the service station/cell in a control region, whereby a start position of the PDSCH allocated for the UE by the service station/cell is the first symbol of a subframe, and when a resource mapping in the control region is performed, the PDSCH does not occupy Resource Elements (REs) occupied by a Cell Reference Signal (CRS), a Physical Control Format Indicator Channel (PCFICH), a Physical Hybrid-ARQ Indicator Channel (PHICH) of a station/cell where the PDSCH is located, and a Physical Downlink Control Channel PDCCH of the UE.

Abstract: Provided are an inter-eNodeB communication method and device, wherein the method includes that: an inter-eNodeB interface transmission condition is detected, a cooperation mode of inter-eNodeB communication is determined according to the inter-eNodeB interface transmission condition, and the inter-eNodeB communication is performed according to the cooperation mode. The present disclosure solves the problem of inter-eNodeB cooperation in different inter-eNodeB interface conditions in the related art, thus improving the effect of the inter-eNodeB cooperation.

Abstract: Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created.

Abstract: Layout simulation and verification of a semiconductor chip can require extensive design rule checking (DRC) and design rules for manufacturing (DRM) analysis of the design in order to ensure proper operation. DRC and DRM can be expensive in terms of computational time and resource usage. To mitigate some of the cost, a virtual layer can be constructed for a cell instance identified in the semiconductor design. Shapes including rectangles and polygons can be determined which traverse the cell instance and are from other hierarchical layers of the design. The shapes can be combined to generate a virtual layer used for simulation, validation, DRC, DRM, etc. The virtual layer can be augmented with traversing shape information from other instances of the cell. The rectangles, polygons, and complex polygons can be combined to simplify the virtual layer. Multiple virtual layers can be generated for the simulation and validation processes.

Abstract: Simulation and verification are critical to analyzing a semiconductor design using design rule checking (DRC) to verify design rules for manufacturing (DRM). The efficient use of computational resources including runtimes and resource requirements is a key component of the analysis. A virtual hierarchical layer (VHL) with shapes is generated for the design analysis of a design, including cells and hierarchical design levels. A cell and multiple instances of the cell are identified in the design. A VHL based on polygons overlapping the cell is generated in response to an algorithmic operation. The VHL shapes are propagated to subsequent algorithmic operations. The algorithmic operations update the VHL shapes. Shapes are filtered out of the VHL shapes as part of the updating. The VHL shapes are propagated through a chain of operations.

Abstract: A method and system are provided for conserving network resources such as battery power of a battery-powered communication device used to support a conversation over a wireless network transport media. Periods of silence are detected during conversation taking place on a network having controllable resources such as battery power. Using the periods of silence so-detected, future silence periods occurring on the network are then predicted. Allocation of at least a portion of the controllable resources is controlled based on the future silence periods so-predicted.

Abstract: A method and system are provided for conserving network resources such as battery power of a battery-powered communication device used to support a conversation over a wireless network transport media. Periods of silence are detected during conversation taking place on a network having controllable resources such as battery power. Using the periods of silence so-detected, future silence periods occurring on the network are then predicted. Allocation of at least a portion of the controllable resources is controlled based on the future silence periods so-predicted.

Abstract: A system and method are provided for parsing a digital video sequence, having a series of frames, into at least one segment including frames having a same camera motion quality category, selected from a predetermined list of possible camera motion quality categories. The method includes obtaining, for each of the frames, at least three pieces of information representative of the motion in the frame. The information includes: translational motion information, representative of translational motion in the frame; rotational motion information, representative of rotational motion in the frame; and scale motion information, representative of scale motion in the frame. The method further includes processing the at least three pieces of information representative of the motion in the frame, to attribute one of the camera motion quality categories to each of the frames.

Abstract: At least one of the scroll members is composed of a metallic insert having substantial the same configuration of the scroll member, i.e. an end plate and spiral wraps fixed to and extended from the end plate. The metallic insert has anchor holes and connecting holes for bonding the plastic coating layer on to the metallic insert. The anchor holes also serve as gas escaping passages during injection molding process. The mold has multiple poring gates to minimize the pressure gradients across the spiral wraps during the injection molding process. The metallic insert has also tubers sticking out from the tip of its spiral wraps. The tubers are firmly held by the mold in the injection molding process to prevent movement of the spiral wraps under the pressure from the injected plastic flow. The metallic inserts can be fully or partially coated by the plastic compound such that there is no metallic to metallic contact between the scroll members during operations.