Abstract: The compound as shown in formula (I) or a pharmaceutically acceptable salt or pharmaceutical composition thereof, and a preparation method therefor, and the use thereof as an MAT2A inhibitor. Ring A, ring Q, X, Y, X1, X2, L and R1 in formula (I) are as defined in the description.

Abstract: The present invention relates to the field of elevator braking, in particular to an action state detection method and system for an elevator brake, comprising: acquiring matching pairs of brake linings in the same braking state; constructing normal record data sets based on the matching pairs; grouping the normal record data sets based on braking power corresponding to samples in the normal record data sets to determine a median of elevator running speed corresponding to the samples in each group; dividing the operating state levels of the elevator brake according to the size of the median; constructing a data training set; training a constructed network model to obtain a trained network model; acquiring the operating state levels of an elevator to be detected by the trained network model, evaluating the elevator brake according to the operating state levels, and controlling the elevator.

Abstract: The present application provides an instruction encoding-based data processing method and apparatus, and a device. N-path error correction encoding is performed on an instruction in information to be processed to obtain N encoded instructions, the encoded instructions and encoded meta channel programs obtained by the error correction encoding are used to perform redundant processing on data to be processed to obtain N pieces of response data, and then error correction decoding is performed on the N pieces of response data to obtain processing result information of the information to be processed. Because the N encoded instructions are heterogeneous and the encoded meta channel programs used in the N-path processing are heterogeneous, the randomness of the processing process can be improved, generalized disturbance in the data processing process can be corrected in combination with the error correction encoding and decoding methods, and thus the security of data processing is improved.

Abstract: A keyboard includes a keyboard base, a key and a driving portion. The key includes a keycap and a key holder, and the driving portion includes a driving board, a first mating member, and a second mating member. The first mating member and the second mating member are arranged on the driving board; the driving board moves in a first direction relative to the keyboard base through the second mating member; and the key includes a key mating member, and when moving in the first direction, the driving board drives the first mating member to move relative to the key mating member to drive the key to descend.

Abstract: A method, apparatus, and a non-transitory computer-readable storage medium for generating heterogenous platform code. The method may obtain a neural network model. The neural network model may be programed to run on at least one platform. The method may also obtain an initial intermediate representation (IR) code by encoding the neural network model, and obtain a target IR code by adding decorations to the initial IR code based on a target platform. The method may also output an executable code optimized to run on the target platform by decoding the target IR code.

Abstract: Disclosed herein are batteries and methods of making batteries. The batteries disclosed herein generally comprise a cathode, an electrolyte capable of conducting protons and/or hydronium ions, and an anode comprising a material capable of absorbing protons and/or hydronium ions, wherein (i) the cathode is in contact with a cathode substance, or (ii) the electrolyte comprises a reduced cathode substance, or (iii) the cathode is in contact with a cathode substance and the electrolyte comprises a reduced cathode substance, and wherein the cathode substance is an oxide of one or more metals or an oxide of a halide.

Abstract: Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created.

Abstract: Layout simulation and verification of a semiconductor chip can require extensive design rule checking (DRC) and design rules for manufacturing (DRM) analysis of the design in order to ensure proper operation. DRC and DRM can be expensive in terms of computational time and resource usage. To mitigate some of the cost, a virtual layer can be constructed for a cell instance identified in the semiconductor design. Shapes including rectangles and polygons can be determined which traverse the cell instance and are from other hierarchical layers of the design. The shapes can be combined to generate a virtual layer used for simulation, validation, DRC, DRM, etc. The virtual layer can be augmented with traversing shape information from other instances of the cell. The rectangles, polygons, and complex polygons can be combined to simplify the virtual layer. Multiple virtual layers can be generated for the simulation and validation processes.

Abstract: Techniques for a mild hybrid vehicle utilize a control system for detecting a deceleration fuel shutoff (DFSO) event where fueling to an engine is disabled and in response to detecting the DFSO event: determining a desired pumping loss for the engine based on a parameter of a battery system, the desired pumping loss corresponding to a desired amount of electrical energy that a motor generator unit (MGU) of a belt-driven starter generator (BSG) system will generate to charge the battery system; commanding a throttle valve of the engine to an initial position determined based on the desired engine pumping loss and a speed of the engine; estimating an actual pumping loss of the engine based on an estimated airflow into the engine; and adjusting the position of the throttle valve based on a difference between the desired and actual engine pumping losses.

Abstract: Provided are an inter-eNodeB communication method and device, wherein the method includes that: an inter-eNodeB interface transmission condition is detected, a cooperation mode of inter-eNodeB communication is determined according to the inter-eNodeB interface transmission condition, and the inter-eNodeB communication is performed according to the cooperation mode. The present disclosure solves the problem of inter-eNodeB cooperation in different inter-eNodeB interface conditions in the related art, thus improving the effect of the inter-eNodeB cooperation.

Abstract: The present document discloses a method, apparatus and system for indicating downlink resources of a coordinated multi-point network in an LTE system. The method includes: determining a control station/cell and a service station/cell of a User Equipment (UE); and indicating through signaling that a Physical Downlink Shared Channel (PDSCH) of the UE occupies radio resources of the service station/cell in a control region, whereby a start position of the PDSCH allocated for the UE by the service station/cell is the first symbol of a subframe, and when a resource mapping in the control region is performed, the PDSCH does not occupy Resource Elements (REs) occupied by a Cell Reference Signal (CRS), a Physical Control Format Indicator Channel (PCFICH), a Physical Hybrid-ARQ Indicator Channel (PHICH) of a station/cell where the PDSCH is located, and a Physical Downlink Control Channel PDCCH of the UE.

Abstract: Simulation and verification are critical to analyzing a semiconductor design using design rule checking (DRC) to verify design rules for manufacturing (DRM). The efficient use of computational resources including runtimes and resource requirements is a key component of the analysis. A virtual hierarchical layer (VHL) with shapes is generated for the design analysis of a design, including cells and hierarchical design levels. A cell and multiple instances of the cell are identified in the design. A VHL based on polygons overlapping the cell is generated in response to an algorithmic operation. The VHL shapes are propagated to subsequent algorithmic operations. The algorithmic operations update the VHL shapes. Shapes are filtered out of the VHL shapes as part of the updating. The VHL shapes are propagated through a chain of operations.

Abstract: Provided are an inter-eNodeB communication method and device, wherein the method includes that: an inter-eNodeB interface transmission condition is detected, a cooperation mode of inter-eNodeB communication is determined according to the inter-eNodeB interface transmission condition, and the inter-eNodeB communication is performed according to the cooperation mode. The present disclosure solves the problem of inter-eNodeB cooperation in different inter-eNodeB interface conditions in the related art, thus improving the effect of the inter-eNodeB cooperation.

Abstract: The present document discloses a method, apparatus and system for indicating downlink resources of a coordinated multi-point network in an LTE system. The method includes: determining a control station/cell and a service station/cell of a User Equipment (UE); and indicating through signaling that a Physical Downlink Shared Channel (PDSCH) of the UE occupies radio resources of the service station/cell in a control region, whereby a start position of the PDSCH allocated for the UE by the service station/cell is the first symbol of a subframe, and when a resource mapping in the control region is performed, the PDSCH does not occupy Resource Elements (REs) occupied by a Cell Reference Signal (CRS), a Physical Control Format Indicator Channel (PCFICH), a Physical Hybrid-ARQ Indicator Channel (PHICH) of a station/cell where the PDSCH is located, and a Physical Downlink Control Channel PDCCH of the UE.

Abstract: Layout simulation and verification of a semiconductor chip can require extensive design rule checking (DRC) and design rules for manufacturing (DRM) analysis of the design in order to ensure proper operation. DRC and DRM can be expensive in terms of computational time and resource usage. To mitigate some of the cost, a virtual layer can be constructed for a cell instance identified in the semiconductor design. Shapes including rectangles and polygons can be determined which traverse the cell instance and are from other hierarchical layers of the design. The shapes can be combined to generate a virtual layer used for simulation, validation, DRC, DRM, etc. The virtual layer can be augmented with traversing shape information from other instances of the cell. The rectangles, polygons, and complex polygons can be combined to simplify the virtual layer. Multiple virtual layers can be generated for the simulation and validation processes.

Abstract: Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created.

Abstract: Simulation and verification are critical to analyzing a semiconductor design using design rule checking (DRC) to verify design rules for manufacturing (DRM). The efficient use of computational resources including runtimes and resource requirements is a key component of the analysis. A virtual hierarchical layer (VHL) with shapes is generated for the design analysis of a design, including cells and hierarchical design levels. A cell and multiple instances of the cell are identified in the design. A VHL based on polygons overlapping the cell is generated in response to an algorithmic operation. The VHL shapes are propagated to subsequent algorithmic operations. The algorithmic operations update the VHL shapes. Shapes are filtered out of the VHL shapes as part of the updating. The VHL shapes are propagated through a chain of operations.

Abstract: A method and system are provided for conserving network resources such as battery power of a battery-powered communication device used to support a conversation over a wireless network transport media. Periods of silence are detected during conversation taking place on a network having controllable resources such as battery power. Using the periods of silence so-detected, future silence periods occurring on the network are then predicted. Allocation of at least a portion of the controllable resources is controlled based on the future silence periods so-predicted.

Abstract: A method and system are provided for conserving network resources such as battery power of a battery-powered communication device used to support a conversation over a wireless network transport media. Periods of silence are detected during conversation taking place on a network having controllable resources such as battery power. Using the periods of silence so-detected, future silence periods occurring on the network are then predicted. Allocation of at least a portion of the controllable resources is controlled based on the future silence periods so-predicted.

Abstract: A system and method are provided for parsing a digital video sequence, having a series of frames, into at least one segment including frames having a same camera motion quality category, selected from a predetermined list of possible camera motion quality categories. The method includes obtaining, for each of the frames, at least three pieces of information representative of the motion in the frame. The information includes: translational motion information, representative of translational motion in the frame; rotational motion information, representative of rotational motion in the frame; and scale motion information, representative of scale motion in the frame. The method further includes processing the at least three pieces of information representative of the motion in the frame, to attribute one of the camera motion quality categories to each of the frames.