Patents by Inventor Zhen-Yu Guan

Zhen-Yu Guan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087906
    Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Zhen Yu Guan, Hsun-Chung Kuang
  • Patent number: 11854822
    Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhen Yu Guan, Hsun-Chung Kuang
  • Publication number: 20230377959
    Abstract: A semiconductor structure including a self-assembled monolayer for enhancing metal-dielectric adhesion and preventing metal diffusion is provided. The semiconductor structure includes a substrate and a first dielectric layer on the substrate. A contact structure is embedded in the first dielectric layer and includes a conductive line. The semiconductor structure further includes a self-assembled monolayer on the conductive line, and a second dielectric layer on the first dielectric layer and the conductive line. The self-assembled monolayer is chemically bonded to the conductive line and the second dielectric layer.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Zhen Yu GUAN, Hsun-Chung KUANG
  • Patent number: 11810817
    Abstract: A semiconductor structure including a self-assembled monolayer for enhancing metal-dielectric adhesion and preventing metal diffusion is provided. The semiconductor structure includes a substrate and a first dielectric layer on the substrate. A contact structure is embedded in the first dielectric layer and includes a conductive line. The semiconductor structure further includes a self-assembled monolayer on the conductive line, and a second dielectric layer on the first dielectric layer and the conductive line. The self-assembled monolayer is chemically bonded to the conductive line and the second dielectric layer.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhen Yu Guan, Hsun-Chung Kuang
  • Publication number: 20230238318
    Abstract: The present disclosure relates integrated chip structure. The integrated chip structure includes a lower insulating structure disposed over a lower dielectric structure surrounding one or more lower interconnects. A bottom electrode via surrounded by one or more interior sidewalls of the lower insulating structure. The bottom electrode via includes a barrier surrounding a conductive core. A bottom electrode is arranged on the bottom electrode via, a data storage structure is over the bottom electrode, and a top electrode is over the data storage structure. The barrier includes a sidewall disposed along the one or more interior sidewalls of the lower insulating structure and a horizontally covering segment protruding outward from the sidewall to above a top surface of the lower insulating structure.
    Type: Application
    Filed: April 21, 2022
    Publication date: July 27, 2023
    Inventors: Zhen Yu Guan, Sheng-Wen Fu, Hsun-Chung Kuang
  • Publication number: 20220293429
    Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 15, 2022
    Inventors: Zhen Yu Guan, Hsun-Chung Kuang
  • Publication number: 20220115267
    Abstract: A semiconductor structure including a self-assembled monolayer for enhancing metal-dielectric adhesion and preventing metal diffusion is provided. The semiconductor structure includes a substrate and a first dielectric layer on the substrate. A contact structure is embedded in the first dielectric layer and includes a conductive line. The semiconductor structure further includes a self-assembled monolayer on the conductive line, and a second dielectric layer on the first dielectric layer and the conductive line. The self-assembled monolayer is chemically bonded to the conductive line and the second dielectric layer.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 14, 2022
    Inventors: Zhen Yu GUAN, Hsun-Chung KUANG
  • Patent number: 10336692
    Abstract: The present invention provides a method of forming paracyclyophane containing disulfide functional group. The paracyclophane is prepared by adding 3,3?-dithiodipropionic acid (DPDPA) and N-ethyl-N?-(3-(dimethylamino)propyl)carbodiimide (EDC) into 4-aminomethyl [2,2] paracyclophane. The present invention further provides a chemical film and a method of forming the same. The chemical film contains poly-p-xylylene with disulfide functional group and is formed on a substrate by a chemical vapor deposition process.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: July 2, 2019
    Assignee: MAY-HWA ENTERPRISE CORPORATION
    Inventors: Hsien-Yeh Chen, Zhen-Yu Guan, Chih-Yu Wu
  • Patent number: 10246412
    Abstract: The present invention provides a method of forming paracyclyophane containing disulfide functional group. The paracyclophane is prepared by adding 3,3?-dithiodipropionic acid (DPDPA) and N-ethyl-N?-(3-(dimethylamino)propyl)carbodiimide (EDC) into 4-aminomethyl [2,2] paracyclophane. The present invention further provides a chemical film and a method of forming the same. The chemical film contains poly-p-xylylene with disulfide functional group and is formed on a substrate by a chemical vapor deposition process.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: April 2, 2019
    Assignee: MAY-HWA ENTERPRISE CORPORATION
    Inventors: Hsien-Yeh Chen, Zhen-Yu Guan, Chih-Yu Wu
  • Publication number: 20180273898
    Abstract: The present invention provides a biological material including a parylene C film; and first proteins which are adsorbed on the surface of the parylene C film. According to an embodiment of the present invention, the biological material further includes second proteins different from the first proteins adsorbed on the surface of the parylene C film. According to an embodiment of the present invention, the first proteins or the second proteins include BMP-2, fibronectin or PRP.
    Type: Application
    Filed: May 4, 2017
    Publication date: September 27, 2018
    Inventors: Hsien-Yeh Chen, Zhen-Yu Guan
  • Publication number: 20180265460
    Abstract: The present invention provides a method of forming paracyclyophane containing disulfide functional group. The paracyclophane is prepared by adding 3,3?-dithiodipropionic acid (DPDPA) and N-ethyl-N?-(3-(dimethylamino)propyl)carbodiimide (EDC) into 4-aminomethyl [2,2] paracyclophane. The present invention further provides a chemical film and a method of forming the same. The chemical film contains poly-p-xylylene with disulfide functional group and is formed on a substrate by a chemical vapor deposition process.
    Type: Application
    Filed: March 7, 2018
    Publication date: September 20, 2018
    Inventors: Hsien-Yeh Chen, Zhen-Yu Guan, Chih-Yu Wu
  • Publication number: 20170166520
    Abstract: The present invention provides a method of forming paracyclyophane containing disulfide functional group. The paracyclophane is prepared by adding 3,3?-dithiodipropionic acid (DPDPA) and N-ethyl-N?-(3-(dimethylamino)propyl)carbodiimide (EDC) into 4-aminomethyl [2,2] paracyclophane. The present invention further provides a chemical film and a method of forming the same. The chemical film contains poly-p-xylylene with disulfide functional group and is formed on a substrate by a chemical vapor deposition process.
    Type: Application
    Filed: June 16, 2016
    Publication date: June 15, 2017
    Inventors: Hsien-Yeh Chen, Zhen-Yu Guan, Chih-Yu Wu