Abstract: An observation is made that the peak voltage value for a rectified AC voltage signal is substantially the same from cycle to cycle. Using this observation, a method of measuring an AC voltage is used to determine a more accurate RMS voltage value under light load conditions. The method includes rectifying the AC voltage signal to form a rectified signal, sampling the rectified signal to obtain a set of sampled values for each half-cycle of the AC voltage signal, searching the sampled values for each half-cycle to determine a local minimum value for each half-cycle, searching the sampled values following the local minimum value to determine a local maximum value for each half-cycle, and calculating a root mean square value from the local maximum value for each half-cycle thereby determining the root mean square value for each half-cycle of the AC voltage signal.

Abstract: A method of optimally generating a power failure warning (PFW) signal has been disclosed here in such a manner that adjusts timing of PFW signal generation according to load conditions in case of input AC voltage loss. A PFW voltage threshold value can be set at a lower value under light load conditions and at a higher value under heavy load conditions. PFW signal generation can also be triggered by a timing mechanism that is set when a bus voltage drops to a voltage threshold value. A countdown time of the timing mechanism is set according to a determined bus voltage drop rate. In this manner, issuance of the PFW signal is delayed for lighter load conditions and the power supply unit is capable of extending normal operation under lighter load conditions before the PFW signal is issued.

Abstract: A switching mode power converter includes a DSC with a digital PWM module configured for complementary operation mode during normal operation. The control algorithm of the DSC is configured such that during an initialization stage immediately following power up of the device relevant digital PWM modules used for interleaving operation are reconfigured to temporarily operate in an independent operation mode with the duty cycle associated with each channel set at zero. The reconfigured digital PWM modules remain set in the independent operation mode for a predefined period of time. Once the predefined time period is reached, the reconfigured digital PWM modules are again reconfigured back to the original complementary operation mode configuration and the control algorithm resumes normal operation of the DSC and digital PWM modules.

Abstract: A controller for estimating a power of a power converter and method of estimating the same has been introduced herein. In one embodiment, the controller includes an analog/digital converter configured to provide samples of a rectified voltage waveform corresponding to a rectified sensed voltage of the power converter. The controller also includes a processor configured to estimate a minimum value of the rectified voltage waveform in accordance with the samples and remove an offset from the rectified voltage waveform to obtain an unbiased rectified voltage waveform in accordance with the estimate of the minimum value. The controller is also configured to obtain an unbiased rectified current waveform corresponding to sensed current of the power converter and provide an average power of the power converter.

Abstract: A controller for estimating a power of a power converter and method of estimating the same has been introduced herein. In one embodiment, the controller includes an analog/digital converter configured to provide samples of a rectified voltage waveform corresponding to a rectified sensed voltage of the power converter. The controller also includes a processor configured to estimate a minimum value of the rectified voltage waveform in accordance with the samples and remove an offset from the rectified voltage waveform to obtain an unbiased rectified voltage waveform in accordance with the estimate of the minimum value. The controller is also configured to obtain an unbiased rectified current waveform corresponding to sensed current of the power converter and provide an average power of the power converter.

Abstract: A method is directed to providing adaptive digital control for the PFC front-end of a switching mode power supply. The method uses an evaluation model to adjust control loop parameters of a control algorithm used by a controller on the primary side of the power supply. The method performs a series of step adjustments of the control loop parameter values to determine optimized values. In some implementations, the method determines and compares the line current THD corresponding to different control loop parameter values. The method provides simplified digital control loop design, optimizes PFC front-end performance, improves system efficiency by decreasing harmonic ripples, and reduces labor cost and time to market due to shorter research and development phase. System performance optimization is fully adaptive adjusted for changes in operating conditions due to, for example, environmental and temperature variations.

Abstract: A robust decoder generates an output state from input signals related to the line-voltage signals of a three-phase power system, using a segment identification method based on zero-crossings derived from line-voltage difference signals. The robust decoder includes a basic decoder that provides a current output state based on the input signals, a state table that provides a presumed previous state based on the current output state of the basic decoder, a binary feed back loop including a state element for storing a previous output state, and a selector for providing the output state based on the stored previous output state and the presumed previous state. The robust decoder may be implemented as hardware or software in a digital power converter.

Abstract: A robust decoder generates an output state from input signals related to the line-voltage signals of a three-phase power system, using a segment identification method based on zero-crossings derived from line-voltage difference signals. The robust decoder includes a basic decoder that provides a current output state based on the input signals, a state table that provides a presumed previous state based on the current output state of the basic decoder, a binary feed back loop including a state element for storing a previous output state, and a selector for providing the output state based on the stored previous output state and the presumed previous state. The robust decoder may be implemented as hardware or software in a digital power converter.